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[50.57.142.19]) by mx.google.com with ESMTPS id p4si1181072igr.51.2014.04.24.15.48.49 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 24 Apr 2014 15:49:02 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WdSPC-0003LW-Hm; Thu, 24 Apr 2014 22:46:10 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WdSPB-0003LM-Kr for xen-devel@lists.xenproject.org; Thu, 24 Apr 2014 22:46:09 +0000 Received: from [85.158.137.68:55014] by server-7.bemta-3.messagelabs.com id 6A/3F-04151-03499535; Thu, 24 Apr 2014 22:46:08 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-13.tower-31.messagelabs.com!1398379567!8895716!1 X-Originating-IP: [74.125.83.48] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 28897 invoked from network); 24 Apr 2014 22:46:08 -0000 Received: from mail-ee0-f48.google.com (HELO mail-ee0-f48.google.com) (74.125.83.48) by server-13.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 24 Apr 2014 22:46:08 -0000 Received: by mail-ee0-f48.google.com with SMTP id b57so2284332eek.21 for ; Thu, 24 Apr 2014 15:46:07 -0700 (PDT) X-Received: by 10.14.221.2 with SMTP id q2mr5178999eep.68.1398379567849; Thu, 24 Apr 2014 15:46:07 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id t44sm19683823eeo.6.2014.04.24.15.46.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Apr 2014 15:46:06 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Thu, 24 Apr 2014 23:45:54 +0100 Message-Id: <1398379556-1132-3-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1398379556-1132-1-git-send-email-julien.grall@linaro.org> References: <1398379556-1132-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH 2/4] xen/arm: Implement a dummy Performance Monitor for ARM32 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: XSA-93 (commit 0b18220 "xen/arm: Don't let guess access to Debug and Performance Monitor registers") disable Performance Monitor. When CONFIG_PERF_EVENTS is enabled in the Linux Kernel, regardless the ID_DFR0 (which tell if Perfomance Monitors Extension is implemented) the kernel will try to access to PMCR. Therefore we tell the guest we have 0 counters. Unfortunately we must always support PMCCNTR (the cycle counter): we just RAZ/WI for all PM register, which doesn't crash the kernel at least. Signed-off-by: Julien Grall --- This commit is candidate for backporting on Xen 4.4. Some distribution (such as Linaro Ubuntu image) enable Perf Events (CONFIG_PERF_EVENTS=y). Linux will unconditionally access to theses registers and therefore will crash. --- xen/arch/arm/traps.c | 28 ++++++++++++++++++++++++++++ xen/include/asm-arm/cpregs.h | 17 ++++++++++++++++- 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 700665c..319bbe9 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1387,6 +1387,34 @@ static void do_cp15_32(struct cpu_user_regs *regs, if ( cp32.read ) *r = v->arch.actlr; break; + + /* We could trap ID_DFR0 and tell the guest we don't support + * performance monitoring, but Linux doesn't check the ID_DFR0. + * Therefore it will read PMCR. + * + * We tell the guest we have 0 counters. Unfortunately we must + * always support PMCCNTR (the cyle counter): we just RAZ/WI for all + * PM register, which doesn't crash the kernel at least + */ + case HSR_CPREG32(PMCR): + case HSR_CPREG32(PMCNTENSET): + case HSR_CPREG32(PMCNTENCLR): + case HSR_CPREG32(PMOVSR): + case HSR_CPREG32(PMSWINC): + case HSR_CPREG32(PMSELR): + case HSR_CPREG32(PMCEID0): + case HSR_CPREG32(PMCEID1): + case HSR_CPREG32(PMCCNTR): + case HSR_CPREG32(PMXEVCNTR): + case HSR_CPREG32(PMXEVCNR): + case HSR_CPREG32(PMUSERENR): + case HSR_CPREG32(PMINTENSET): + case HSR_CPREG32(PMINTENCLR): + case HSR_CPREG32(PMOVSSET): + if ( cp32.read ) + *r = 0; + break; + default: #ifndef NDEBUG gdprintk(XENLOG_ERR, diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index bf8133e..f44e3b5 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -198,7 +198,22 @@ #define TLBIMVAH p15,4,c8,c7,1 /* Invalidate Unified Hyp. TLB by MVA */ #define TLBIALLNSNH p15,4,c8,c7,4 /* Invalidate Entire Non-Secure Non-Hyp. Unified TLB */ -/* CP15 CR9: */ +/* CP15 CR9: Performance monitors */ +#define PMCR p15,0,c9,c12,0 /* Perf. Mon. Control Register */ +#define PMCNTENSET p15,0,c9,c12,1 /* Perf. Mon. Count Enable Set register */ +#define PMCNTENCLR p15,0,c9,c12,2 /* Perf. Mon. Count Enable Clear register */ +#define PMOVSR p15,0,c9,c12,3 /* Perf. Mon. Overflow Flag Status Register */ +#define PMSWINC p15,0,c9,c12,4 /* Perf. Mon. Software Increment register */ +#define PMSELR p15,0,c9,c12,5 /* Perf. Mon. Event Counter Selection Register */ +#define PMCEID0 p15,0,c9,c12,6 /* Perf. Mon. Common Event Identification register 0 */ +#define PMCEID1 p15,0,c9,c12,7 /* Perf. Mon. Common Event Identification register 1 */ +#define PMCCNTR p15,0,c9,c13,0 /* Perf. Mon. Cycle Count Register */ +#define PMXEVCNTR p15,0,c9,c13,1 /* Perf. Mon. Event Type Select Register */ +#define PMXEVCNR p15,0,c9,c13,2 /* Perf. Mon. Event Count Register */ +#define PMUSERENR p15,0,c9,c14,0 /* Perf. Mon. User Enable Register */ +#define PMINTENSET p15,0,c9,c14,1 /* Perf. Mon. Interrupt Enable Set Register */ +#define PMINTENCLR p15,0,c9,c14,2 /* Perf. Mon. Interrupt Enable Clear Register */ +#define PMOVSSET p15,0,c9,c14,3 /* Perf. Mon. Overflow Flag Status Set register */ /* CP15 CR10: */ #define MAIR0 p15,0,c10,c2,0 /* Memory Attribute Indirection Register 0 AKA PRRR */