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[50.57.142.19]) by mx.google.com with ESMTPS id af10si6889064vec.23.2014.04.22.06.16.35 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 22 Apr 2014 06:16:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WcaXv-0006Rn-MC; Tue, 22 Apr 2014 13:15:35 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WcaXj-0006F7-IK for xen-devel@lists.xenproject.org; Tue, 22 Apr 2014 13:15:23 +0000 Received: from [85.158.137.68:6207] by server-3.bemta-3.messagelabs.com id 26/81-05289-86B66535; Tue, 22 Apr 2014 13:15:20 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-8.tower-31.messagelabs.com!1398172519!3201335!1 X-Originating-IP: [74.125.83.54] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3870 invoked from network); 22 Apr 2014 13:15:19 -0000 Received: from mail-ee0-f54.google.com (HELO mail-ee0-f54.google.com) (74.125.83.54) by server-8.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 22 Apr 2014 13:15:19 -0000 Received: by mail-ee0-f54.google.com with SMTP id d49so4703795eek.27 for ; Tue, 22 Apr 2014 06:15:19 -0700 (PDT) X-Received: by 10.14.4.69 with SMTP id 45mr12706152eei.66.1398172519470; Tue, 22 Apr 2014 06:15:19 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id 45sm112969867eeh.9.2014.04.22.06.15.17 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Apr 2014 06:15:17 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 22 Apr 2014 14:14:32 +0100 Message-Id: <1398172475-27873-19-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1398172475-27873-1-git-send-email-julien.grall@linaro.org> References: <1398172475-27873-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v4 18/21] xen/arm: p2m: Clean cache PT when the IOMMU doesn't support coherent walk X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Some IOMMU doesn't suppport coherent PT walk. When the p2m is shared with the CPU, Xen has to make sure the PT changes have reached the memory. Introduce new IOMMU callback that will retrieve the IOMMU feature for a specified domain. On ARM, the platform can contain multiple IOMMUs. Each of them may not have the same set of feature. The domain parameter will be used to get the set of features for IOMMUs used by this domain. Signed-off-by: Julien Grall --- Changes in v4: - Patch added --- xen/arch/arm/p2m.c | 24 ++++++++++++++++++------ xen/drivers/passthrough/iommu.c | 11 +++++++++++ xen/include/xen/iommu.h | 5 +++++ 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 21219de..996d2bd 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -274,6 +274,18 @@ enum p2m_operation { CACHEFLUSH, }; +static void unmap_coherent_domain_page(struct domain *d, const void *va) +{ + /* Some IOMMU doesn't support coherent PT walk. When the p2m is + * shared with the CPU, Xen has to make sure that the PT changes have + * reached the memory + */ + if ( need_iommu(d) && !iommu_has_feature(d, IOMMU_FEAT_COHERENT_WALK) ) + clean_xen_dcache_va_range(va, PAGE_SIZE); + + unmap_domain_page(va); +} + static int apply_p2m_changes(struct domain *d, enum p2m_operation op, paddr_t start_gpaddr, @@ -301,7 +313,7 @@ static int apply_p2m_changes(struct domain *d, { if ( cur_first_page != p2m_first_level_index(addr) ) { - if ( first ) unmap_domain_page(first); + if ( first ) unmap_coherent_domain_page(d, first); first = p2m_map_first(p2m, addr); if ( !first ) { @@ -331,7 +343,7 @@ static int apply_p2m_changes(struct domain *d, if ( cur_first_offset != first_table_offset(addr) ) { - if (second) unmap_domain_page(second); + if (second) unmap_coherent_domain_page(d, second); second = map_domain_page(first[first_table_offset(addr)].p2m.base); cur_first_offset = first_table_offset(addr); } @@ -357,7 +369,7 @@ static int apply_p2m_changes(struct domain *d, if ( cur_second_offset != second_table_offset(addr) ) { /* map third level */ - if (third) unmap_domain_page(third); + if (third) unmap_coherent_domain_page(d, third); third = map_domain_page(second[second_table_offset(addr)].p2m.base); cur_second_offset = second_table_offset(addr); } @@ -480,9 +492,9 @@ static int apply_p2m_changes(struct domain *d, rc = 0; out: - if (third) unmap_domain_page(third); - if (second) unmap_domain_page(second); - if (first) unmap_domain_page(first); + if (third) unmap_coherent_domain_page(d, third); + if (second) unmap_coherent_domain_page(d, second); + if (first) unmap_coherent_domain_page(d, first); spin_unlock(&p2m->lock); diff --git a/xen/drivers/passthrough/iommu.c b/xen/drivers/passthrough/iommu.c index f93dc79..f24fb46 100644 --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -344,6 +344,17 @@ void iommu_crash_shutdown(void) iommu_enabled = iommu_intremap = 0; } +bool_t iommu_has_feature(struct domain *d, uint32_t feature) +{ + const struct iommu_ops *ops = domain_hvm_iommu(d)->platform_ops; + uint32_t features = 0; + + if ( iommu_enabled && ops && ops->features ) + features = ops->features(d); + + return !!(features & feature); +} + static void iommu_dump_p2m_table(unsigned char key) { struct domain *d; diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index e119379..9ad909f 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -67,6 +67,10 @@ int iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn, unsigned int flags); int iommu_unmap_page(struct domain *d, unsigned long gfn); +#define IOMMU_FEAT_COHERENT_WALK (1U<<0) +bool_t iommu_has_feature(struct domain *d, uint32_t feature); + + #ifdef HAS_PCI void pt_pci_init(void); @@ -139,6 +143,7 @@ struct iommu_ops { void (*iotlb_flush)(struct domain *d, unsigned long gfn, unsigned int page_count); void (*iotlb_flush_all)(struct domain *d); void (*dump_p2m_table)(struct domain *d); + uint32_t (*features)(struct domain *d); }; void iommu_suspend(void);