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[50.57.142.19]) by mx.google.com with ESMTPS id em3si16801928qcb.65.2014.04.22.06.04.41 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 22 Apr 2014 06:04:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WcaLS-0002WB-4U; Tue, 22 Apr 2014 13:02:42 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WcaIc-0001iB-FK for xen-devel@lists.xenproject.org; Tue, 22 Apr 2014 12:59:46 +0000 Received: from [85.158.143.35:19935] by server-2.bemta-4.messagelabs.com id B7/4F-06539-1A766535; Tue, 22 Apr 2014 12:59:13 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-14.tower-21.messagelabs.com!1398171550!252511!1 X-Originating-IP: [74.125.83.46] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3558 invoked from network); 22 Apr 2014 12:59:11 -0000 Received: from mail-ee0-f46.google.com (HELO mail-ee0-f46.google.com) (74.125.83.46) by server-14.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 22 Apr 2014 12:59:11 -0000 Received: by mail-ee0-f46.google.com with SMTP id t10so4531038eei.5 for ; Tue, 22 Apr 2014 05:59:10 -0700 (PDT) X-Received: by 10.15.53.135 with SMTP id r7mr2126354eew.102.1398171550767; Tue, 22 Apr 2014 05:59:10 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id x45sm112862825eef.15.2014.04.22.05.59.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Apr 2014 05:59:10 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 22 Apr 2014 13:58:42 +0100 Message-Id: <1398171530-27391-11-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1398171530-27391-1-git-send-email-julien.grall@linaro.org> References: <1398171530-27391-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v4 10/18] xen/arm: IRQ: Require desc.lock be held by callers of hw_irq_controller callbacks X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: When multiple action are supported, gic_irq_{startup,shutdown} will have to be called in the same critical section as setup/release. Otherwise there is a race condition if at the same time CPU A is calling release_dt_irq and CPU B is calling setup_dt_irq. This could end up with the IRQ not being enabled. At the same time, modify gic_irq_{enable,disable} to require desc.lock be held. With both of theses changes, ARM's locking requirements is the same as x86's. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Changes in v4: - Fix typo in commit message - Don't depend on Stefano's interrupt series (will likely be pushed before) Changes in v3: - Update commit message - Require desc.lock also for gic_irq_{enable,disable} - irqflags is unsigned long not unsigned int Changes in v2: - Fix typoes in commit message - Move this patch earlier in the series => move shutdown() in release_irq and gic_route_irq --- xen/arch/arm/gic.c | 21 +++++++++++---------- xen/arch/arm/irq.c | 6 ++++-- xen/arch/arm/vgic.c | 10 ++++++++++ 3 files changed, 25 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 77dfecf..29ecb49 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -128,14 +128,14 @@ static void gic_irq_enable(struct irq_desc *desc) int irq = desc->irq; unsigned long flags; - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&gic.lock); + ASSERT(spin_is_locked(&desc->lock)); + + spin_lock_irqsave(&gic.lock, flags); desc->status &= ~IRQ_DISABLED; dsb(sy); /* Enable routing */ GICD[GICD_ISENABLER + irq / 32] = (1u << (irq % 32)); - spin_unlock(&gic.lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&gic.lock, flags); } static void gic_irq_disable(struct irq_desc *desc) @@ -143,18 +143,19 @@ static void gic_irq_disable(struct irq_desc *desc) int irq = desc->irq; unsigned long flags; - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&gic.lock); + ASSERT(spin_is_locked(&desc->lock)); + + spin_lock_irqsave(&gic.lock, flags); /* Disable routing */ GICD[GICD_ICENABLER + irq / 32] = (1u << (irq % 32)); desc->status |= IRQ_DISABLED; - spin_unlock(&gic.lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&gic.lock, flags); } static unsigned int gic_irq_startup(struct irq_desc *desc) { gic_irq_enable(desc); + return 0; } @@ -261,11 +262,11 @@ static int gic_route_irq(unsigned int irq, bool_t level, if ( desc->action != NULL ) return -EBUSY; + spin_lock_irqsave(&desc->lock, flags); + /* Disable interrupt */ desc->handler->shutdown(desc); - spin_lock_irqsave(&desc->lock, flags); - desc->handler = &gic_host_irq_type; gic_set_irq_properties(irq, level, cpu_mask, priority); diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 26574ca..b6dd9de 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -217,9 +217,10 @@ void release_irq(unsigned int irq) desc = irq_to_desc(irq); + spin_lock_irqsave(&desc->lock,flags); + desc->handler->shutdown(desc); - spin_lock_irqsave(&desc->lock,flags); action = desc->action; desc->action = NULL; desc->status &= ~IRQ_GUEST; @@ -254,11 +255,12 @@ int setup_dt_irq(const struct dt_irq *irq, struct irqaction *new) spin_lock_irqsave(&desc->lock, flags); rc = __setup_irq(desc, new); - spin_unlock_irqrestore(&desc->lock, flags); if ( !rc ) desc->handler->startup(desc); + spin_unlock_irqrestore(&desc->lock, flags); + return rc; } diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 4a7f8c0..1b95003 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -374,6 +374,7 @@ static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) const unsigned long mask = r; struct pending_irq *p; unsigned int irq; + unsigned long flags; int i = 0; while ( (i = find_next_bit(&mask, 32, i)) < 32 ) { @@ -382,7 +383,11 @@ static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) clear_bit(GIC_IRQ_GUEST_ENABLED, &p->status); gic_remove_from_queues(v, irq); if ( p->desc != NULL ) + { + spin_lock_irqsave(&p->desc->lock, flags); p->desc->handler->disable(p->desc); + spin_unlock_irqrestore(&p->desc->lock, flags); + } i++; } } @@ -392,6 +397,7 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) const unsigned long mask = r; struct pending_irq *p; unsigned int irq; + unsigned long flags; int i = 0; while ( (i = find_next_bit(&mask, 32, i)) < 32 ) { @@ -401,7 +407,11 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) gic_set_guest_irq(v, irq, GICH_LR_PENDING, p->priority); if ( p->desc != NULL ) + { + spin_lock_irqsave(&p->desc->lock, flags); p->desc->handler->enable(p->desc); + spin_unlock_irqrestore(&p->desc->lock, flags); + } i++; } }