From patchwork Tue Apr 8 14:43:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 27991 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f69.google.com (mail-oa0-f69.google.com [209.85.219.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0FF1720447 for ; Tue, 8 Apr 2014 14:45:57 +0000 (UTC) Received: by mail-oa0-f69.google.com with SMTP id i7sf4530586oag.4 for ; Tue, 08 Apr 2014 07:45:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:cc:subject:precedence:list-id:list-unsubscribe:list-post :list-help:list-subscribe:mime-version:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list :list-archive:content-type:content-transfer-encoding; bh=U+PTbJK2Wg3twx5R8GZjRR8n06Ps+eR3ieNT4YKseVg=; b=Hm3zJ0bf6CgXg2eu9C8EKjN/5Jc16jwh0/awIMEGOA27rzmwXQ/2T7CiUhSJKdauN4 mCBgr0l2kOH8VubIPdNE94Oh1W6rGIVNhehrcUDjhne5f3m/+LelZv6SZiCBVQDnD5jT xUjAiHNWTkWkMgRNxBjvN1B2LS6NXCxaxuO8qijQXaHBTrp3ifhO16d7BSxyLF3tbxxu cWfLIUzqB5o71oQL2pz7e/SCDlOPjUA5dZrmgzF4JrJoCRCN1oP6lktIVwBXuDNaZ7FV h6RRmzBcFT5ulmb78FINYGWmmQ26nICUsweJUgS2F3LKGNlEBweho+OtQRT/Wf+ww9re 9ttw== X-Gm-Message-State: ALoCoQlLDAJpzuxXeqnrlr56GEVRFSrS19lJ7WkqOZEj0CgECmyhr5J/r7w2bKnYoRFUSzZso+nr X-Received: by 10.182.95.68 with SMTP id di4mr2089062obb.4.1396968357594; Tue, 08 Apr 2014 07:45:57 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.41.40 with SMTP id y37ls222151qgy.10.gmail; Tue, 08 Apr 2014 07:45:57 -0700 (PDT) X-Received: by 10.58.211.69 with SMTP id na5mr637401vec.30.1396968357441; Tue, 08 Apr 2014 07:45:57 -0700 (PDT) Received: from mail-ve0-f175.google.com (mail-ve0-f175.google.com [209.85.128.175]) by mx.google.com with ESMTPS id uq6si439710vcb.0.2014.04.08.07.45.57 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Apr 2014 07:45:57 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.175; Received: by mail-ve0-f175.google.com with SMTP id oz11so850930veb.34 for ; Tue, 08 Apr 2014 07:45:57 -0700 (PDT) X-Received: by 10.58.123.71 with SMTP id ly7mr3614779veb.11.1396968357356; Tue, 08 Apr 2014 07:45:57 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.12.8 with SMTP id v8csp251664vcv; Tue, 8 Apr 2014 07:45:56 -0700 (PDT) X-Received: by 10.140.29.131 with SMTP id b3mr4789912qgb.5.1396968355720; Tue, 08 Apr 2014 07:45:55 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id a3si927906qat.166.2014.04.08.07.45.55 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 08 Apr 2014 07:45:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WXXGI-0000Jv-Lx; Tue, 08 Apr 2014 14:44:30 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WXXGF-0000G3-7h for xen-devel@lists.xenproject.org; Tue, 08 Apr 2014 14:44:27 +0000 Received: from [193.109.254.147:8610] by server-1.bemta-14.messagelabs.com id 88/F1-00839-A4B04435; Tue, 08 Apr 2014 14:44:26 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-6.tower-27.messagelabs.com!1396968264!7039251!1 X-Originating-IP: [74.125.83.51] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23791 invoked from network); 8 Apr 2014 14:44:24 -0000 Received: from mail-ee0-f51.google.com (HELO mail-ee0-f51.google.com) (74.125.83.51) by server-6.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 8 Apr 2014 14:44:24 -0000 Received: by mail-ee0-f51.google.com with SMTP id c13so767221eek.24 for ; Tue, 08 Apr 2014 07:44:23 -0700 (PDT) X-Received: by 10.14.104.135 with SMTP id i7mr4994681eeg.34.1396968263912; Tue, 08 Apr 2014 07:44:23 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id m42sm5031709eex.21.2014.04.08.07.44.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Apr 2014 07:44:23 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 8 Apr 2014 15:43:59 +0100 Message-Id: <1396968247-8768-11-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396968247-8768-1-git-send-email-julien.grall@linaro.org> References: <1396968247-8768-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v3 10/18] xen/arm: IRQ: Require desc.lock held by callers of hw_irq_controller callbacks X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: When multiple action are supported, gic_irq_{startup,shutdown} will have to be called in the same critical section as setup/release. Otherwise there is a race condition if at the same time CPU A is calling release_dt_irq and CPU B is calling setup_dt_irq. This could end up with the IRQ not being enabled. At the same time, modify gic_irq_{enable,disable} to require desc.lock held. With this both changes, ARM's locking requirements is the same as x86's. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Changes in v3: - Update commit message - Require desc.lock also for gic_irq_{enable,disable} - irqflags is unsigned long not unsigned int Changes in v2: - Fix typoes in commit message - Move this patch earlier in the series => move shutdown() in release_irq and gic_route_irq --- xen/arch/arm/gic.c | 21 +++++++++++---------- xen/arch/arm/irq.c | 6 ++++-- xen/arch/arm/vgic.c | 11 ++++++++++- 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 5f16fe6..cbef41f 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -132,14 +132,14 @@ static void gic_irq_enable(struct irq_desc *desc) int irq = desc->irq; unsigned long flags; - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&gic.lock); + ASSERT(spin_is_locked(&desc->lock)); + + spin_lock_irqsave(&gic.lock, flags); desc->status &= ~IRQ_DISABLED; dsb(sy); /* Enable routing */ GICD[GICD_ISENABLER + irq / 32] = (1u << (irq % 32)); - spin_unlock(&gic.lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&gic.lock, flags); } static void gic_irq_disable(struct irq_desc *desc) @@ -147,18 +147,19 @@ static void gic_irq_disable(struct irq_desc *desc) int irq = desc->irq; unsigned long flags; - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&gic.lock); + ASSERT(spin_is_locked(&desc->lock)); + + spin_lock_irqsave(&gic.lock, flags); /* Disable routing */ GICD[GICD_ICENABLER + irq / 32] = (1u << (irq % 32)); desc->status |= IRQ_DISABLED; - spin_unlock(&gic.lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&gic.lock, flags); } static unsigned int gic_irq_startup(struct irq_desc *desc) { gic_irq_enable(desc); + return 0; } @@ -265,11 +266,11 @@ static int gic_route_irq(unsigned int irq, bool_t level, if ( desc->action != NULL ) return -EBUSY; + spin_lock_irqsave(&desc->lock, flags); + /* Disable interrupt */ desc->handler->shutdown(desc); - spin_lock_irqsave(&desc->lock, flags); - desc->handler = &gic_host_irq_type; gic_set_irq_properties(irq, level, cpu_mask, priority); diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 9320ac7..2d7a9e5 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -214,9 +214,10 @@ void release_irq(unsigned int irq) desc = irq_to_desc(irq); + spin_lock_irqsave(&desc->lock,flags); + desc->handler->shutdown(desc); - spin_lock_irqsave(&desc->lock,flags); action = desc->action; desc->action = NULL; desc->status &= ~IRQ_GUEST; @@ -251,11 +252,12 @@ int setup_dt_irq(const struct dt_irq *irq, struct irqaction *new) spin_lock_irqsave(&desc->lock, flags); rc = __setup_irq(desc, new); - spin_unlock_irqrestore(&desc->lock, flags); if ( !rc ) desc->handler->startup(desc); + spin_unlock_irqrestore(&desc->lock, flags); + return rc; } diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 8616534..b5e919e 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -374,6 +374,7 @@ static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) const unsigned long mask = r; struct pending_irq *p; unsigned int irq; + unsigned long flags; int i = 0; while ( (i = find_next_bit(&mask, 32, i)) < 32 ) { @@ -382,7 +383,11 @@ static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) clear_bit(GIC_IRQ_GUEST_ENABLED, &p->status); gic_remove_from_queues(v, irq); if ( p->desc != NULL ) + { + spin_lock_irqsave(&p->desc->lock, flags); p->desc->handler->disable(p->desc); + spin_unlock_irqrestore(&p->desc->lock, flags); + } i++; } } @@ -392,6 +397,7 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) const unsigned long mask = r; struct pending_irq *p; unsigned int irq; + unsigned long flags; int i = 0; while ( (i = find_next_bit(&mask, 32, i)) < 32 ) { @@ -403,14 +409,17 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) list_empty(&p->inflight) ) vgic_vcpu_inject_irq(v, irq); else { - unsigned long flags; spin_lock_irqsave(&v->arch.vgic.lock, flags); if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) gic_raise_guest_irq(v, irq, p->priority); spin_unlock_irqrestore(&v->arch.vgic.lock, flags); } if ( p->desc != NULL ) + { + spin_lock_irqsave(&p->desc->lock, flags); p->desc->handler->enable(p->desc); + spin_unlock_irqrestore(&p->desc->lock, flags); + } i++; } }