From patchwork Thu Apr 3 20:42:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 27715 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-bk0-f70.google.com (mail-bk0-f70.google.com [209.85.214.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 7A09B20490 for ; Thu, 3 Apr 2014 20:44:43 +0000 (UTC) Received: by mail-bk0-f70.google.com with SMTP id my13sf2626706bkb.5 for ; Thu, 03 Apr 2014 13:44:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:cc:subject:precedence:list-id:list-unsubscribe:list-post :list-help:list-subscribe:mime-version:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list :list-archive:content-type:content-transfer-encoding; bh=SQ2pIEnVM/Cg1MRk95x+qs3+ioq6wK/5wZZMvCL3uNs=; b=KHMYtz5ro1Acp0WhHovuLnbelsoBsS3q53HKxgVw2Gr9BJerwLthVbzRP/Af8mlKjc b0mlb9cvcReAxz5Ogs2S4JHkniVzDFsFmxPRBdf0l4iNTec/CTsro7Z6e1juO7fHYOne 5VjDgBZFcsTf6gvkOmCAk8e1zLKeJTuz/LhGh0d1RoTf/mJpwtq2W8kTAMn95PbIOSaX jYCGMMTaKjalPCcvitcCNYCta9rbm2T5QVs5e1Q2D+6gYJ5dSQcM+zk7s4yB9aguR3nm YlabobEo6wSzFIrZ1o1PrrFV29oLyC+6X0jeOANqHKOPQAXPHCJmwtTIYLiU80P48jYK TT0Q== X-Gm-Message-State: ALoCoQk3Z1js9nMIHSAvaC198tSlK+Z6pW6J4LJKKUiT38xGoufs4A1mUnuyBv1C8us+vBEZ4NrU X-Received: by 10.180.89.5 with SMTP id bk5mr1727205wib.0.1396557882320; Thu, 03 Apr 2014 13:44:42 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.47.197 with SMTP id m63ls828673qga.58.gmail; Thu, 03 Apr 2014 13:44:42 -0700 (PDT) X-Received: by 10.220.162.6 with SMTP id t6mr4623109vcx.12.1396557882207; Thu, 03 Apr 2014 13:44:42 -0700 (PDT) Received: from mail-ve0-f178.google.com (mail-ve0-f178.google.com [209.85.128.178]) by mx.google.com with ESMTPS id bj3si1416547vcb.64.2014.04.03.13.44.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 03 Apr 2014 13:44:42 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.178; Received: by mail-ve0-f178.google.com with SMTP id jw12so714415veb.23 for ; Thu, 03 Apr 2014 13:44:42 -0700 (PDT) X-Received: by 10.220.250.203 with SMTP id mp11mr4595752vcb.2.1396557882124; Thu, 03 Apr 2014 13:44:42 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.12.8 with SMTP id v8csp59825vcv; Thu, 3 Apr 2014 13:44:41 -0700 (PDT) X-Received: by 10.140.82.167 with SMTP id h36mr9550517qgd.51.1396557880968; Thu, 03 Apr 2014 13:44:40 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id g2si2639836qab.61.2014.04.03.13.44.40 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 03 Apr 2014 13:44:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVoTE-0008HV-9y; Thu, 03 Apr 2014 20:42:44 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVoTC-0008G1-9d for xen-devel@lists.xenproject.org; Thu, 03 Apr 2014 20:42:42 +0000 Received: from [193.109.254.147:24583] by server-15.bemta-14.messagelabs.com id A1/0D-15813-1C7CD335; Thu, 03 Apr 2014 20:42:41 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-11.tower-27.messagelabs.com!1396557760!6109776!1 X-Originating-IP: [74.125.82.180] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3218 invoked from network); 3 Apr 2014 20:42:40 -0000 Received: from mail-we0-f180.google.com (HELO mail-we0-f180.google.com) (74.125.82.180) by server-11.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 3 Apr 2014 20:42:40 -0000 Received: by mail-we0-f180.google.com with SMTP id p61so2415279wes.25 for ; Thu, 03 Apr 2014 13:42:40 -0700 (PDT) X-Received: by 10.180.102.97 with SMTP id fn1mr14463806wib.15.1396557759950; Thu, 03 Apr 2014 13:42:39 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id t50sm14510572eev.28.2014.04.03.13.42.38 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Apr 2014 13:42:39 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Thu, 3 Apr 2014 21:42:04 +0100 Message-Id: <1396557727-19102-14-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396557727-19102-1-git-send-email-julien.grall@linaro.org> References: <1396557727-19102-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v2 13/16] xen/arm: IRQ: Store IRQ type in arch_irq_desc X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: For now, ARM uses different IRQ functions to setup an interrupt handler. This is a bit annoying for common driver because we have to add idefery when an IRQ is setup (see ns16550_init_postirq for an example). To avoid to completely fork the IRQ management code, we can introduce a field to store the IRQ type (e.g level/edge ...). This patch also adds platform_get_irq which will retrieve the IRQ from the device tree and setup correctly the IRQ type. In order to use this solution, we have to move init_IRQ earlier for the boot CPU. It's fine because the code only depends on percpu. Signed-off-by: Julien Grall --- Changes in v2: - Patch added --- xen/arch/arm/gic.c | 21 +++++++----- xen/arch/arm/irq.c | 80 ++++++++++++++++++++++++++++++++++++++++----- xen/arch/arm/setup.c | 3 +- xen/include/asm-arm/gic.h | 5 ++- xen/include/asm-arm/irq.h | 3 ++ 5 files changed, 91 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 9127ecf..ec2994e 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -223,15 +223,20 @@ static hw_irq_controller gic_guest_irq_type = { /* * - needs to be called with a valid cpu_mask, ie each cpu in the mask has + * - desc.lock must be held * already called gic_cpu_init */ -static void gic_set_irq_properties(unsigned int irq, bool_t level, +static void gic_set_irq_properties(struct irq_desc *desc, const cpumask_t *cpu_mask, unsigned int priority) { volatile unsigned char *bytereg; uint32_t cfg, edgebit; unsigned int mask; + unsigned int irq = desc->irq; + unsigned int type = desc->arch.type; + + ASSERT(spin_is_locked(&desc->lock)); spin_lock(&gic.lock); @@ -240,7 +245,7 @@ static void gic_set_irq_properties(unsigned int irq, bool_t level, /* Set edge / level */ cfg = GICD[GICD_ICFGR + irq / 16]; edgebit = 2u << (2 * (irq % 16)); - if ( level ) + if ( (type & DT_IRQ_TYPE_LEVEL_MASK) || (type == DT_IRQ_TYPE_NONE) ) cfg &= ~edgebit; else cfg |= edgebit; @@ -260,8 +265,8 @@ static void gic_set_irq_properties(unsigned int irq, bool_t level, /* Program the GIC to route an interrupt to the host (eg Xen) * - needs to be called with desc.lock held */ -void gic_route_irq_to_xen(struct irq_desc *desc, bool_t level, - const cpumask_t *cpu_mask, unsigned int priority) +void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, + unsigned int priority) { ASSERT(priority <= 0xff); /* Only 8 bits of priority */ ASSERT(desc->irq < gic.lines);/* Can't route interrupts that don't exist */ @@ -270,15 +275,14 @@ void gic_route_irq_to_xen(struct irq_desc *desc, bool_t level, desc->handler = &gic_host_irq_type; - gic_set_irq_properties(desc->irq, level, cpu_mask, priority); + gic_set_irq_properties(desc, cpu_mask, priority); } /* Program the GIC to route an interrupt to a guest * - desc.lock must be held */ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc, - bool_t level, const cpumask_t *cpu_mask, - unsigned int priority) + const cpumask_t *cpu_mask, unsigned int priority) { struct pending_irq *p; ASSERT(spin_is_locked(&desc->lock)); @@ -286,8 +290,7 @@ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc, desc->handler = &gic_guest_irq_type; desc->status |= IRQ_GUEST; - gic_set_irq_properties(desc->irq, level, cpumask_of(smp_processor_id()), - GIC_PRI_IRQ); + gic_set_irq_properties(desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ); /* TODO: do not assume delivery to vcpu0 */ p = irq_to_pending(d->vcpu[0], desc->irq); diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 2bf6618..a56ccf2 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -55,6 +55,7 @@ irq_desc_t *__irq_to_desc(int irq) int __init arch_init_one_irq_desc(struct irq_desc *desc) { + desc->arch.type = DT_IRQ_TYPE_NONE; return 0; } @@ -82,6 +83,12 @@ static int __cpuinit init_local_irq_data(void) init_one_irq_desc(desc); desc->irq = irq; desc->action = NULL; + + /* PPIs are include in local_irqs, we have to copy the IRQ type from + * CPU0 otherwise we may miss the type if the IRQ type has been + * set early. + */ + desc->arch.type = per_cpu(local_irq_desc, 0)[irq].arch.type; } return 0; @@ -272,9 +279,6 @@ int setup_dt_irq(const struct dt_irq *irq, struct irqaction *new) /* First time the IRQ is setup */ if ( disabled ) { - bool_t level; - - level = dt_irq_is_level_triggered(irq); /* It's fine to use smp_processor_id() because: * For PPI: irq_desc is banked * For SPI: we don't care for now which CPU will receive the @@ -282,7 +286,8 @@ int setup_dt_irq(const struct dt_irq *irq, struct irqaction *new) * TODO: Handle case where SPI is setup on different CPU than * the targeted CPU and the priority. */ - gic_route_irq_to_xen(desc, level, cpumask_of(smp_processor_id()), + desc->arch.type = irq->type; + gic_route_irq_to_xen(desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ); desc->handler->startup(desc); } @@ -300,7 +305,6 @@ int route_dt_irq_to_guest(struct domain *d, const struct dt_irq *irq, struct irq_desc *desc = irq_to_desc(irq->irq); unsigned long flags; int retval = 0; - bool_t level; action = xmalloc(struct irqaction); if (!action) @@ -341,10 +345,9 @@ int route_dt_irq_to_guest(struct domain *d, const struct dt_irq *irq, goto out; } - level = dt_irq_is_level_triggered(irq); - gic_route_irq_to_guest(d, desc, level, cpumask_of(smp_processor_id()), + desc->arch.type = irq->type; + gic_route_irq_to_guest(d, desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ); - out: spin_unlock_irqrestore(&desc->lock, flags); return retval; @@ -379,6 +382,67 @@ void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) BUG(); } +static inline int irq_set_type(struct irq_desc *desc, unsigned int type) +{ + unsigned int flags; + int ret = -EBUSY; + + if ( type == DT_IRQ_TYPE_NONE ) + return 0; + + spin_lock_irqsave(&desc->lock, flags); + + if ( desc->arch.type != DT_IRQ_TYPE_NONE && desc->arch.type != type ) + goto err; + + desc->arch.type = type; + + ret = 0; + +err: + spin_unlock_irqrestore(&desc->lock, flags); + return ret; +} + +unsigned int platform_get_irq(const struct dt_device_node *device, + int index) +{ + struct dt_irq dt_irq; + struct irq_desc *desc; + unsigned int type, irq; + int res; + + res = dt_device_get_irq(device, index, &dt_irq); + if ( res ) + return 0; + + irq = dt_irq.irq; + type = dt_irq.type; + + /* Setup the IRQ type */ + + if ( irq < NR_LOCAL_IRQS ) + { + unsigned int cpu; + /* For PPIs, we need to set IRQ type on every online CPUs */ + for_each_cpu( cpu, &cpu_online_map ) + { + desc = &per_cpu(local_irq_desc, cpu)[irq]; + res = irq_set_type(desc, type); + if ( res ) + return 0; + } + } + else + { + res = irq_set_type(irq_to_desc(irq), type); + if ( res ) + return 0; + } + + return irq; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 7b02282..b755964 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -687,6 +687,8 @@ void __init start_xen(unsigned long boot_phys_offset, dt_unflatten_host_device_tree(); dt_irq_xlate = gic_irq_xlate; + init_IRQ(); + dt_uart_init(); console_init_preirq(); @@ -716,7 +718,6 @@ void __init start_xen(unsigned long boot_phys_offset, tasklet_subsys_init(); - init_IRQ(); xsm_dt_init(); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index b750b17..80f8dd2 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -168,11 +168,10 @@ extern void vgic_clear_pending_irqs(struct vcpu *v); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); /* Program the GIC to route an interrupt */ -extern void gic_route_irq_to_xen(struct irq_desc *desc, bool_t level, - const cpumask_t *cpu_mask, +extern void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, unsigned int priority); extern void gic_route_irq_to_guest(struct domain *, struct irq_desc *desc, - bool_t level, const cpumask_t *cpu_mask, + const cpumask_t *cpu_mask, unsigned int priority); extern void gic_inject(void); diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index b52c26f..107c13a 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -16,6 +16,7 @@ struct arch_pirq struct arch_irq_desc { int eoi_cpu; + unsigned int type; }; #define NR_LOCAL_IRQS 32 @@ -46,6 +47,8 @@ int setup_dt_irq(const struct dt_irq *irq, struct irqaction *new); int route_dt_irq_to_guest(struct domain *d, const struct dt_irq *irq, const char *devname); +unsigned int platform_get_irq(const struct dt_device_node *device, + int index); #endif /* _ASM_HW_IRQ_H */ /*