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[50.57.142.19]) by mx.google.com with ESMTPS id vd8si604979vdc.52.2014.04.02.08.04.13 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 02 Apr 2014 08:04:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVMg0-0004tl-Qy; Wed, 02 Apr 2014 15:02:04 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVMfz-0004tR-OR for xen-devel@lists.xensource.com; Wed, 02 Apr 2014 15:02:03 +0000 Received: from [85.158.143.35:48049] by server-1.bemta-4.messagelabs.com id 4D/32-09853-B662C335; Wed, 02 Apr 2014 15:02:03 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-15.tower-21.messagelabs.com!1396450920!5795894!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 19162 invoked from network); 2 Apr 2014 15:02:02 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-15.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 2 Apr 2014 15:02:02 -0000 X-IronPort-AV: E=Sophos;i="4.97,780,1389744000"; d="scan'208";a="117348305" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 02 Apr 2014 15:02:00 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Wed, 2 Apr 2014 11:01:58 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WVMfp-0003fd-6Q; Wed, 02 Apr 2014 16:01:53 +0100 From: Stefano Stabellini To: Date: Wed, 2 Apr 2014 16:01:39 +0100 Message-ID: <1396450906-542-3-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v6 03/10] xen/arm: set GICH_HCR_UIE if all the LRs are in use X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On return to guest, if there are no free LRs and we still have more interrupt to inject, set GICH_HCR_UIE so that we are going to receive a maintenance interrupt when no pending interrupts are present in the LR registers. The maintenance interrupt handler won't do anything anymore, but receiving the interrupt is going to cause gic_inject to be called on return to guest that is going to clear the old LRs and inject new interrupts. Signed-off-by: Stefano Stabellini Acked-by: Julien Grall --- Changes in v5: - introduce lr_all_full() helper. Changes in v2: - disable/enable the GICH_HCR_UIE bit in GICH_HCR; - only enable GICH_HCR_UIE if this_cpu(lr_mask) == ((1 << nr_lrs) - 1). --- xen/arch/arm/gic.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index dbba5d3..a7b29d8 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -57,6 +57,7 @@ static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc); static DEFINE_PER_CPU(uint64_t, lr_mask); static unsigned nr_lrs; +#define lr_all_full() (this_cpu(lr_mask) == ((1 << nr_lrs) - 1)) /* The GIC mapping of CPU interfaces does not necessarily match the * logical CPU numbering. Let's use mapping as returned by the GIC @@ -738,6 +739,11 @@ void gic_inject(void) vgic_vcpu_inject_irq(current, current->domain->arch.evtchn_irq); gic_restore_pending_irqs(current); + + if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) + GICH[GICH_HCR] |= GICH_HCR_UIE; + else + GICH[GICH_HCR] &= ~GICH_HCR_UIE; } int gic_route_irq_to_guest(struct domain *d, const struct dt_irq *irq,