From patchwork Wed Apr 2 14:12:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Campbell X-Patchwork-Id: 27619 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f200.google.com (mail-ie0-f200.google.com [209.85.223.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 07E9020490 for ; Wed, 2 Apr 2014 14:14:58 +0000 (UTC) Received: by mail-ie0-f200.google.com with SMTP id lx4sf1265415iec.3 for ; Wed, 02 Apr 2014 07:14:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-post:list-help:list-subscribe:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:list-archive:content-type:content-transfer-encoding; bh=b0W7XLgIUv6alJbLNs6KivqcJeCWME9GbI5k+cE/NY4=; b=L/1aKjygzexaU4R9TRF/X8oHpjgV4WvbNi2fiFft3qPHCClDEGSUznlG4zfS+vyKSj A3KLQq2rlAWMu8QoU2n1skAro5IJoO2EBmD6IWekivjB8gHg60/z86gkyVHO4K+D9zfZ an5luW0YxgbFS2cAsdnsOM4AaBlVQtyizuz0W2leK/oLawgXZcHmMbbNu1k4ncYjouMc kLyEyVn3vJ+mXoJkn0+KLFSwAzJoBh9nTBBt/8LZCk396nfiXlX5IyRldAKOlpSNVnGU o5Jg1M+b8N7MEeUaQQVMKoY8Sna252LGJF7CTBFTTrzkP0qPORsPTbl01pFhTGpZvfYx dWhA== X-Gm-Message-State: ALoCoQlb4OoN87eSZX+quDTiz0vvRjLZANpThKLkoI8W3mKuiwyo0XG1eN4RNQavld67moBnplkZ X-Received: by 10.43.78.135 with SMTP id zm7mr391973icb.27.1396448098303; Wed, 02 Apr 2014 07:14:58 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.26.119 with SMTP id 110ls334035qgu.20.gmail; Wed, 02 Apr 2014 07:14:58 -0700 (PDT) X-Received: by 10.53.11.37 with SMTP id ef5mr803992vdd.62.1396448098213; Wed, 02 Apr 2014 07:14:58 -0700 (PDT) Received: from mail-vc0-f181.google.com (mail-vc0-f181.google.com [209.85.220.181]) by mx.google.com with ESMTPS id fv9si570467vcb.20.2014.04.02.07.14.58 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 02 Apr 2014 07:14:58 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.181; Received: by mail-vc0-f181.google.com with SMTP id id10so371147vcb.12 for ; Wed, 02 Apr 2014 07:14:58 -0700 (PDT) X-Received: by 10.52.33.176 with SMTP id s16mr699830vdi.49.1396448098076; Wed, 02 Apr 2014 07:14:58 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.12.8 with SMTP id v8csp326785vcv; Wed, 2 Apr 2014 07:14:57 -0700 (PDT) X-Received: by 10.140.18.175 with SMTP id 44mr757382qgf.105.1396448097640; Wed, 02 Apr 2014 07:14:57 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id k67si840033qge.114.2014.04.02.07.14.57 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 02 Apr 2014 07:14:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVLui-0000Hd-A0; Wed, 02 Apr 2014 14:13:12 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVLuh-0000H4-7I for xen-devel@lists.xen.org; Wed, 02 Apr 2014 14:13:11 +0000 Received: from [193.109.254.147:51129] by server-11.bemta-14.messagelabs.com id 73/99-09902-5FA1C335; Wed, 02 Apr 2014 14:13:09 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-13.tower-27.messagelabs.com!1396447983!5804029!2 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 11555 invoked from network); 2 Apr 2014 14:13:05 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-13.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 2 Apr 2014 14:13:05 -0000 X-IronPort-AV: E=Sophos;i="4.97,780,1389744000"; d="scan'208";a="116106264" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 02 Apr 2014 14:12:53 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.2.342.4; Wed, 2 Apr 2014 10:12:51 -0400 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WVLuN-00046T-HM; Wed, 02 Apr 2014 14:12:51 +0000 From: Ian Campbell To: Date: Wed, 2 Apr 2014 15:12:50 +0100 Message-ID: <1396447971-27846-2-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396447908.8667.346.camel@kazak.uk.xensource.com> References: <1396447908.8667.346.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH 2/3] xen: arm: flush TLB on all CPUs when setting or clearing fixmaps X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: These mappings are global and therefore need flushing on all processors. Add flush_all_xen_data_tlb_range_va which accomplishes this. Signed-off-by: Ian Campbell --- v3: use dsb(sy) not dsb() --- xen/arch/arm/mm.c | 4 ++-- xen/include/asm-arm/arm32/page.h | 19 +++++++++++++++++++ xen/include/asm-arm/arm64/page.h | 19 +++++++++++++++++++ 3 files changed, 40 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index d523f77..b966a5c 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -215,7 +215,7 @@ void set_fixmap(unsigned map, unsigned long mfn, unsigned attributes) pte.pt.table = 1; /* 4k mappings always have this bit set */ pte.pt.xn = 1; write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte); - flush_xen_data_tlb_range_va_local(FIXMAP_ADDR(map), PAGE_SIZE); + flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE); } /* Remove a mapping from a fixmap entry */ @@ -223,7 +223,7 @@ void clear_fixmap(unsigned map) { lpae_t pte = {0}; write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte); - flush_xen_data_tlb_range_va_local(FIXMAP_ADDR(map), PAGE_SIZE); + flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE); } #ifdef CONFIG_DOMAIN_PAGE diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index b0a2025..2b2bbe6 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -82,6 +82,25 @@ static inline void flush_xen_data_tlb_range_va_local(unsigned long va, isb(); } +/* + * Flush a range of VA's hypervisor mappings from the data TLB on all + * processors in the inner-shareable domain. This is not sufficient + * when changing code mappings or for self modifying code. + */ +static inline void flush_xen_data_tlb_range_va(unsigned long va, + unsigned long size) +{ + unsigned long end = va + size; + dsb(sy); /* Ensure preceding are visible */ + while ( va < end ) { + asm volatile(STORE_CP32(0, TLBIMVAHIS) + : : "r" (va) : "memory"); + va += PAGE_SIZE; + } + dsb(sy); /* Ensure completion of the TLB flush */ + isb(); +} + /* Ask the MMU to translate a VA for us */ static inline uint64_t __va_to_par(vaddr_t va) { diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 65332a3..fdc652c 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -74,6 +74,25 @@ static inline void flush_xen_data_tlb_range_va_local(unsigned long va, isb(); } +/* + * Flush a range of VA's hypervisor mappings from the data TLB of all + * processors in the inner-shareable domain. This is not sufficient + * when changing code mappings or for self modifying code. + */ +static inline void flush_xen_data_tlb_range_va(unsigned long va, + unsigned long size) +{ + unsigned long end = va + size; + dsb(sy); /* Ensure preceding are visible */ + while ( va < end ) { + asm volatile("tlbi vae2is, %0;" + : : "r" (va>>PAGE_SHIFT) : "memory"); + va += PAGE_SIZE; + } + dsb(sy); /* Ensure completion of the TLB flush */ + isb(); +} + /* Ask the MMU to translate a VA for us */ static inline uint64_t __va_to_par(vaddr_t va) {