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[50.57.142.19]) by mx.google.com with ESMTPS id cx4si1265980vcb.5.2014.02.07.04.14.40 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 07 Feb 2014 04:14:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WBkIq-0008LC-L4; Fri, 07 Feb 2014 12:13:04 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WBkIo-0008Jl-DC for xen-devel@lists.xen.org; Fri, 07 Feb 2014 12:13:02 +0000 Received: from [193.109.254.147:30792] by server-1.bemta-14.messagelabs.com id C4/6A-15438-DCDC4F25; Fri, 07 Feb 2014 12:13:01 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-12.tower-27.messagelabs.com!1391775179!2754574!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 30170 invoked from network); 7 Feb 2014 12:13:00 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-12.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 7 Feb 2014 12:13:00 -0000 X-IronPort-AV: E=Sophos;i="4.95,800,1384300800"; d="scan'208";a="98945535" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 07 Feb 2014 12:12:58 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Fri, 7 Feb 2014 07:12:57 -0500 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WBkIj-0002qV-6c; Fri, 07 Feb 2014 12:12:57 +0000 From: Ian Campbell To: Date: Fri, 7 Feb 2014 12:12:56 +0000 Message-ID: <1391775176-30313-5-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1391775139.2162.88.camel@kazak.uk.xensource.com> References: <1391775139.2162.88.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH v4 5/5] xen: arm: correct terminology for cache flush macros X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.43 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: The term "flush" is slightly ambiguous. The correct ARM term for for this operaton is clean, as opposed to clean+invalidate for which we also now have a function. This is a pure rename, no functional change. Signed-off-by: Ian Campbell Acked-by: Julien Grall --- This could easily be left for 4.5. --- xen/arch/arm/guestcopy.c | 2 +- xen/arch/arm/kernel.c | 2 +- xen/arch/arm/mm.c | 16 ++++++++-------- xen/arch/arm/smpboot.c | 2 +- xen/include/asm-arm/arm32/page.h | 2 +- xen/include/asm-arm/arm64/page.h | 2 +- xen/include/asm-arm/page.h | 10 +++++----- 7 files changed, 18 insertions(+), 18 deletions(-) diff --git a/xen/arch/arm/guestcopy.c b/xen/arch/arm/guestcopy.c index bd0a355..af0af6b 100644 --- a/xen/arch/arm/guestcopy.c +++ b/xen/arch/arm/guestcopy.c @@ -24,7 +24,7 @@ static unsigned long raw_copy_to_guest_helper(void *to, const void *from, p += offset; memcpy(p, from, size); if ( flush_dcache ) - flush_xen_dcache_va_range(p, size); + clean_xen_dcache_va_range(p, size); unmap_domain_page(p - offset); len -= size; diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index 6a5772b..1e3107d 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -58,7 +58,7 @@ void copy_from_paddr(void *dst, paddr_t paddr, unsigned long len, int attrindx) set_fixmap(FIXMAP_MISC, p, attrindx); memcpy(dst, src + s, l); - flush_xen_dcache_va_range(dst, l); + clean_xen_dcache_va_range(dst, l); paddr += l; dst += l; diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index d2cfe64..4c5cff0 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -480,13 +480,13 @@ void __init setup_pagetables(unsigned long boot_phys_offset, paddr_t xen_paddr) /* Clear the copy of the boot pagetables. Each secondary CPU * rebuilds these itself (see head.S) */ memset(boot_pgtable, 0x0, PAGE_SIZE); - flush_xen_dcache(boot_pgtable); + clean_xen_dcache(boot_pgtable); #ifdef CONFIG_ARM_64 memset(boot_first, 0x0, PAGE_SIZE); - flush_xen_dcache(boot_first); + clean_xen_dcache(boot_first); #endif memset(boot_second, 0x0, PAGE_SIZE); - flush_xen_dcache(boot_second); + clean_xen_dcache(boot_second); /* Break up the Xen mapping into 4k pages and protect them separately. */ for ( i = 0; i < LPAE_ENTRIES; i++ ) @@ -524,7 +524,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset, paddr_t xen_paddr) /* Make sure it is clear */ memset(this_cpu(xen_dommap), 0, DOMHEAP_SECOND_PAGES*PAGE_SIZE); - flush_xen_dcache_va_range(this_cpu(xen_dommap), + clean_xen_dcache_va_range(this_cpu(xen_dommap), DOMHEAP_SECOND_PAGES*PAGE_SIZE); #endif } @@ -535,7 +535,7 @@ int init_secondary_pagetables(int cpu) /* Set init_ttbr for this CPU coming up. All CPus share a single setof * pagetables, but rewrite it each time for consistency with 32 bit. */ init_ttbr = (uintptr_t) xen_pgtable + phys_offset; - flush_xen_dcache(init_ttbr); + clean_xen_dcache(init_ttbr); return 0; } #else @@ -570,15 +570,15 @@ int init_secondary_pagetables(int cpu) write_pte(&first[first_table_offset(DOMHEAP_VIRT_START+i*FIRST_SIZE)], pte); } - flush_xen_dcache_va_range(first, PAGE_SIZE); - flush_xen_dcache_va_range(domheap, DOMHEAP_SECOND_PAGES*PAGE_SIZE); + clean_xen_dcache_va_range(first, PAGE_SIZE); + clean_xen_dcache_va_range(domheap, DOMHEAP_SECOND_PAGES*PAGE_SIZE); per_cpu(xen_pgtable, cpu) = first; per_cpu(xen_dommap, cpu) = domheap; /* Set init_ttbr for this CPU coming up */ init_ttbr = __pa(first); - flush_xen_dcache(init_ttbr); + clean_xen_dcache(init_ttbr); return 0; } diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index c53c765..a829957 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -378,7 +378,7 @@ int __cpu_up(unsigned int cpu) /* Open the gate for this CPU */ smp_up_cpu = cpu_logical_map(cpu); - flush_xen_dcache(smp_up_cpu); + clean_xen_dcache(smp_up_cpu); rc = arch_cpu_up(cpu); diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index cb6add4..b8221ca 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -20,7 +20,7 @@ static inline void write_pte(lpae_t *p, lpae_t pte) } /* Inline ASM to flush dcache on register R (may be an inline asm operand) */ -#define __flush_xen_dcache_one(R) STORE_CP32(R, DCCMVAC) +#define __clean_xen_dcache_one(R) STORE_CP32(R, DCCMVAC) /* Inline ASM to clean and invalidate dcache on register R (may be an * inline asm operand) */ diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index baf8903..3352821 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -15,7 +15,7 @@ static inline void write_pte(lpae_t *p, lpae_t pte) } /* Inline ASM to flush dcache on register R (may be an inline asm operand) */ -#define __flush_xen_dcache_one(R) "dc cvac, %" #R ";" +#define __clean_xen_dcache_one(R) "dc cvac, %" #R ";" /* Inline ASM to clean and invalidate dcache on register R (may be an * inline asm operand) */ diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 67d64c9..a577942 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -229,26 +229,26 @@ extern size_t cacheline_bytes; /* Function for flushing medium-sized areas. * if 'range' is large enough we might want to use model-specific * full-cache flushes. */ -static inline void flush_xen_dcache_va_range(void *p, unsigned long size) +static inline void clean_xen_dcache_va_range(void *p, unsigned long size) { void *end; dsb(); /* So the CPU issues all writes to the range */ for ( end = p + size; p < end; p += cacheline_bytes ) - asm volatile (__flush_xen_dcache_one(0) : : "r" (p)); + asm volatile (__clean_xen_dcache_one(0) : : "r" (p)); dsb(); /* So we know the flushes happen before continuing */ } /* Macro for flushing a single small item. The predicate is always * compile-time constant so this will compile down to 3 instructions in * the common case. */ -#define flush_xen_dcache(x) do { \ +#define clean_xen_dcache(x) do { \ typeof(x) *_p = &(x); \ if ( sizeof(x) > MIN_CACHELINE_BYTES || sizeof(x) > alignof(x) ) \ - flush_xen_dcache_va_range(_p, sizeof(x)); \ + clean_xen_dcache_va_range(_p, sizeof(x)); \ else \ asm volatile ( \ "dsb sy;" /* Finish all earlier writes */ \ - __flush_xen_dcache_one(0) \ + __clean_xen_dcache_one(0) \ "dsb sy;" /* Finish flush before continuing */ \ : : "r" (_p), "m" (*_p)); \ } while (0)