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[50.57.142.19]) by mx.google.com with ESMTPS id 31si866989qgw.134.2014.01.24.06.25.07 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 24 Jan 2014 06:25:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1W6hf7-000815-Aa; Fri, 24 Jan 2014 14:23:13 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1W6hf6-000810-AQ for xen-devel@lists.xen.org; Fri, 24 Jan 2014 14:23:12 +0000 Received: from [85.158.143.35:53843] by server-3.bemta-4.messagelabs.com id F2/82-32360-F4772E25; Fri, 24 Jan 2014 14:23:11 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-5.tower-21.messagelabs.com!1390573389!557469!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3138 invoked from network); 24 Jan 2014 14:23:11 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-5.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 24 Jan 2014 14:23:11 -0000 X-IronPort-AV: E=Sophos;i="4.95,712,1384300800"; d="scan'208";a="96175131" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 24 Jan 2014 14:23:09 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.2.342.4; Fri, 24 Jan 2014 09:23:09 -0500 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1W6hf1-0006YZ-SQ; Fri, 24 Jan 2014 14:23:07 +0000 From: Ian Campbell To: Date: Fri, 24 Jan 2014 14:23:07 +0000 Message-ID: <1390573387-15386-1-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH] xen: arm: correct use of find_next_bit X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: find_next_bit takes a "const unsigned long *" but forcing a cast of an "uint32_t *" throws away the alignment constraints and ends up causing an alignment fault on arm64 if the input happened to be 4 but not 8 byte aligned. Instead of casting use a temporary variable of the right type. I've had a look around for similar constructs and the only thing I found was maintenance_interrupt which cases a uint64_t down to an unsigned long, which although perhaps not best advised is safe I think. This was observed with the AArch64 Linaro toolchain 2013.12 but I think that is just coincidental due to subtle changes to the stack layout etc. Reported-by: Fu Wei Signed-off-by: Ian Campbell Acked-by: Julien Grall --- xen/arch/arm/vgic.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 90e9707..553411d 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -362,11 +362,12 @@ read_as_zero: static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) { + const unsigned long mask = r; struct pending_irq *p; unsigned int irq; int i = 0; - while ( (i = find_next_bit((const long unsigned int *) &r, 32, i)) < 32 ) { + while ( (i = find_next_bit(&mask, 32, i)) < 32 ) { irq = i + (32 * n); p = irq_to_pending(v, irq); clear_bit(GIC_IRQ_GUEST_ENABLED, &p->status); @@ -379,11 +380,12 @@ static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) { + const unsigned long mask = r; struct pending_irq *p; unsigned int irq; int i = 0; - while ( (i = find_next_bit((const long unsigned int *) &r, 32, i)) < 32 ) { + while ( (i = find_next_bit(&mask, 32, i)) < 32 ) { irq = i + (32 * n); p = irq_to_pending(v, irq); set_bit(GIC_IRQ_GUEST_ENABLED, &p->status);