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[50.57.142.19]) by mx.google.com with ESMTPS id fb12si1798549veb.14.2014.01.15.07.00.43 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 15 Jan 2014 07:00:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1W3Rvs-0001ga-LI; Wed, 15 Jan 2014 14:59:04 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1W3Rvq-0001gJ-Oi for xen-devel@lists.xen.org; Wed, 15 Jan 2014 14:59:02 +0000 Received: from [193.109.254.147:26345] by server-13.bemta-14.messagelabs.com id 4C/BF-19374-632A6D25; Wed, 15 Jan 2014 14:59:02 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-3.tower-27.messagelabs.com!1389797939!11040461!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8426 invoked from network); 15 Jan 2014 14:59:01 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-3.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 15 Jan 2014 14:59:01 -0000 X-IronPort-AV: E=Sophos;i="4.95,663,1384300800"; d="scan'208";a="90984847" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 15 Jan 2014 14:58:22 +0000 Received: from [10.80.2.80] (10.80.2.80) by FTLPEX01CL02.citrite.net (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Wed, 15 Jan 2014 09:58:22 -0500 Message-ID: <1389797901.3793.71.camel@kazak.uk.xensource.com> From: Ian Campbell To: Julien Grall Date: Wed, 15 Jan 2014 14:58:21 +0000 In-Reply-To: <52D58692.8000305@linaro.org> References: <1389718504-1514-1-git-send-email-ian.campbell@citrix.com> <52D58692.8000305@linaro.org> Organization: Citrix Systems, Inc. X-Mailer: Evolution 3.4.4-3 MIME-Version: 1.0 X-Originating-IP: [10.80.2.80] X-DLP: MIA2 Cc: stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org Subject: Re: [Xen-devel] [PATCH] xen: arm: correctly write release target in smp_spin_table_cpu_up X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.47 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On Tue, 2014-01-14 at 18:48 +0000, Julien Grall wrote: > On 01/14/2014 04:55 PM, Ian Campbell wrote: > > flush_xen_data_tlb_range_va() is clearly bogus since it flushes the tlb, not > > the data cache. Perhaps what was meant was flush_xen_dcache(), but the address > > was mapped with ioremap_nocache and hence isn't cached in the first place. > > Accesses should be via writeq though, so do that. > > > > Signed-off-by: Ian Campbell > Acked-by: Julien Grall Thanks. I think release wise this can wait for 4.5, the flush is unnecessary but not harmful. While the use of writeq is needed for the additional barriers which it adds it's not strictly needed here because there is no prior write to sequence against (and ioremap_nocache has a barrier in it). Unless removing this pointless flush makes some analysis of the use of the functions less confusing perhaps? However thinking about the writeq barriers to lead me to notice the lack of a recommended dsb() before the subsequent use of sev(), which is needed to ensure that the write has occurred before we wake the other processor. We get away with this because the iounmap in the middle does a write_pte which has a dsb in it. Phew! Still. for 4.5: 8<----- >From aab391b98760cc8417e06512848cf83dd5d71b5c Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Wed, 15 Jan 2014 14:49:04 +0000 Subject: [PATCH] xen: arm: add barrier before sev in smp_spin_table_cpu_up This ensures that the writeq to the release address has occurred. In reality there is a dsb() in the iounmap() (in the e entual write_pte()) but make it explicit. The ARMv8 ARM recommends that sev() is usually accompanied by a dsb(), the only other uses are in the v7 spinlock code which includes a dsb() already. Signed-off-by: Ian Campbell --- xen/arch/arm/arm64/smpboot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/arm/arm64/smpboot.c b/xen/arch/arm/arm64/smpboot.c index 9146476..9c7bf29 100644 --- a/xen/arch/arm/arm64/smpboot.c +++ b/xen/arch/arm/arm64/smpboot.c @@ -36,6 +36,7 @@ static int __init smp_spin_table_cpu_up(int cpu) iounmap(release); + dsb(); sev(); return cpu_up_send_sgi(cpu);