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([185.25.64.249]) by mx.google.com with ESMTPSA id b41sm7127152eef.16.2014.01.09.08.58.05 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Jan 2014 08:58:06 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Cc: patches@linaro.org, ian.campbell@citrix.com, tim@xen.org, stefano.stabellini@citrix.com, Julien Grall Subject: [PATCH] xen/arm: correct flush_tlb_mask behaviour Date: Thu, 9 Jan 2014 16:58:03 +0000 Message-Id: <1389286683-11656-1-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On ARM, flush_tlb_mask is used in the common code: - alloc_heap_pages: the flush is only be called if the new allocated page was used by a domain before. So we need to flush only TLB non-secure non-hyp inner-shareable. - common/grant-table.c: every calls to flush_tlb_mask are used with the current domain. A flush TLB by current VMID inner-shareable is enough. The current code only flush hypervisor TLB on the current PCPU. For now, flush TLBs non-secure non-hyp on every PCPUs. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- This patch is bug fix for Xen 4.4. We were safe because there is already a flush in create_p2m_entries if the previous mapping was valid. For Xen 4.5, we should optimize the function to avoid flush for every VMIDs each time we allocated a new page. --- xen/arch/arm/smp.c | 3 ++- xen/include/asm-arm/arm32/flushtlb.h | 11 +++++++++++ xen/include/asm-arm/arm64/flushtlb.h | 11 +++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index 4042db5..30203b8 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -4,11 +4,12 @@ #include #include #include +#include void flush_tlb_mask(const cpumask_t *mask) { /* No need to IPI other processors on ARM, the processor takes care of it. */ - flush_xen_data_tlb(); + flush_tlb_all(); } void smp_send_event_check_mask(const cpumask_t *mask) diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h index ab166f3..7183a07 100644 --- a/xen/include/asm-arm/arm32/flushtlb.h +++ b/xen/include/asm-arm/arm32/flushtlb.h @@ -34,6 +34,17 @@ static inline void flush_tlb_all_local(void) isb(); } +/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ +static inline void flush_tlb_all(void) +{ + dsb(); + + WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS); + + dsb(); + isb(); +} + #endif /* __ASM_ARM_ARM32_FLUSHTLB_H__ */ /* * Local variables: diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h index 9ce79a8..a73df92 100644 --- a/xen/include/asm-arm/arm64/flushtlb.h +++ b/xen/include/asm-arm/arm64/flushtlb.h @@ -34,6 +34,17 @@ static inline void flush_tlb_all_local(void) : : : "memory"); } +/* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ +static inline void flush_tlb_all(void) +{ + asm volatile( + "dsb sy;" + "tlbi alle1is;" + "dsb sy;" + "isb;" + : : : "memory"); +} + #endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */ /* * Local variables: