From patchwork Tue Jun 27 13:21:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 106421 Delivered-To: patch@linaro.org Received: by 10.140.101.48 with SMTP id t45csp1197465qge; Tue, 27 Jun 2017 06:22:22 -0700 (PDT) X-Received: by 10.237.34.39 with SMTP id n36mr6295093qtc.29.1498569742292; Tue, 27 Jun 2017 06:22:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498569742; cv=none; d=google.com; s=arc-20160816; b=D7IftvpulFM+naLEMp1RIVGd0xu1pvpbh8FiJLVIo9A26C1DafVbGDpEC4M9u1l74c l5qzijwSCTuHicZv0RCOygis41A11MUJOusAe/O96f5goQt/eDbOzAD2DybT+aR3r8XJ yy8zmp3PlSBzch5mLX0iDS4HE4/5iMvz9A+ar5n2P7ltb+q3Bcj/k8rBvoWmeW/KzVDz s6Ov1MJjsK3KakpLf4dRA8F2a4sGZv0SeT/gBeieErvtyZ2Kl9zAA56bZa6vTC3KuwCx oAIl6xNFBiXlXcVPkQLXF6V8xU8Dbs0yUPJYGkDt897WIymZ7QDZr8Ryh66H8HHq1rRZ hb2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=bnF8BM/A3BPxh6Oe+tOUAXOq/TgrcLHI8xweJbqA3I4=; b=dRG5xiH8H+0aBTYmKKOoRdrpNvakDlve/6L84a33X3snMsUi0Tj0quHULfKTUiZqwk XZhrMyei1ZTxPl9CaZEHzAgWMK3SocM/it9mTM7C8elqTNhVUQXCHTubzmXyJJkJh+QP zsImGFjbSgy7+vNd3g7UeAy8cFVz9ZWKuHoR8APrD4ED/cy2Y3R0BgBHKNZ58TGI8+Y6 r/ZdqQZs2HLcMvaY5sHEgq9GvLJ+0DBsfAYNYSifSRAozu+OxUltIgyptcK3gG4pVfOq U09jRYL8WjsWVqh5VYxSnJAXnkogDb9uUr/EpmZ9Lrn0KFtYY0fX06GqPGEi/Byua4vD nrxg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id n188si2683781qkb.292.2017.06.27.06.22.21; Tue, 27 Jun 2017 06:22:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id AFECB60D45; Tue, 27 Jun 2017 13:22:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 1BA6060C1C; Tue, 27 Jun 2017 13:22:01 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 1417560BF8; Tue, 27 Jun 2017 13:21:59 +0000 (UTC) Received: from mail-wr0-f177.google.com (mail-wr0-f177.google.com [209.85.128.177]) by lists.linaro.org (Postfix) with ESMTPS id 0295F60BF4 for ; Tue, 27 Jun 2017 13:21:58 +0000 (UTC) Received: by mail-wr0-f177.google.com with SMTP id k67so158571503wrc.2 for ; Tue, 27 Jun 2017 06:21:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=usQ5WTkCobnYF8CeIHGAFym8ub4eUm2XdAlmsPG0a0k=; b=VCK/+0paf+0OtRGwToiHHu+nvm5maBb+YpP4WCRnGog6y2PQJUKBlo70dPKlYkx53x ADnLZvDBjEFVk2avzaz0hHLFzgyxh76MgYwI7ciATaMWp2eD2raKVV3tM14uyEEXuA18 3EtfTzokBVZCqpClpFdCTF7PUY31bNTmnbj4A4o5pIAwBjh13xJKOUQXT/UBI5iBKd/b Mdj49ZQuYYjegozILjmSRHMoLO+ELrKnxdcKh4e/G1DNNkNWgNCigc2/9QKakqOdY4Ni qGdpY4odpZW7owcnCNaLgbP6HoTvE7N+N2VLehZiU/wh4VClldkfgacB14OkIs01dYiu 7Wlg== X-Gm-Message-State: AKS2vOxQLG/RpRPI6A6laE2fMzJKfLU9/Nepvq2zQVavzRN4ph0bhCLQ M9B/ku7zcc9kbHDoI+T6n5p5 X-Received: by 10.223.131.162 with SMTP id 31mr13641378wre.161.1498569716800; Tue, 27 Jun 2017 06:21:56 -0700 (PDT) Received: from localhost.localdomain ([105.133.250.69]) by smtp.gmail.com with ESMTPSA id p99sm18801062wrb.6.2017.06.27.06.21.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Jun 2017 06:21:56 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Tue, 27 Jun 2017 13:21:36 +0000 Message-Id: <20170627132145.28159-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170627132145.28159-1-ard.biesheuvel@linaro.org> References: <20170627132145.28159-1-ard.biesheuvel@linaro.org> Cc: rfranz@cavium.com, alan@softiron.co.uk Subject: [Linaro-uefi] [PATCH v2 01/10] Platforms/AMD/Styx: remove incorrect timer frequency X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The ARM generic timer needs to be programmed with the actual frequency of the input clock, but this can only be done from the most privileged execution mode implemented by the hardware. UEFI on AArch64 usually executes in EL2, which is not the most privileged execution mode in most cases, and so the timer driver is set up to deal with this: no attempt is made to program the PCD value PcdArmArchTimerFreqInHz into the frequency register. However, a non-zero PCD value is still treated as an override for the register value, in case the programmed value is known to be incorrect. However, on the various Styx based platforms, the PCD value is set to an incorrect non-zero value, and so the routines that convert time delays into cycle counts are off by 33% (187.5 MHz vs 250 MHz). This may affect timeouts related to SATA link training, and other low level routines that rely on accurate timekeeping. So remove the explicit PCD settings, so they default to 0, letting the driver use the programmed value instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 5 ----- Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc | 5 ----- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 5 ----- 3 files changed, 15 deletions(-) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index f068713bf0b8..ddb944d0beb4 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -400,11 +400,6 @@ DEFINE DO_KCS = 0 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000 # - # ARM Architectual Timer Frequency - # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000 - - # # Cello has 2 SATA ports on the first controller. # gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2 diff --git a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc index b1a7cfd4c4a8..f6d2d37014dd 100644 --- a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc @@ -402,11 +402,6 @@ DEFINE DO_KCS = 1 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000 # - # ARM Architectual Timer Frequency - # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000 - - # # 2 ports active on Overdrive 1000 # gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2 diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 98f5c9452dcd..7ac3ce3760fa 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -409,11 +409,6 @@ DEFINE DO_KCS = 1 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000 # - # ARM Architectual Timer Frequency - # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000 - - # # Overdrive B1 has 14 SATA ports across 2 controllers. # gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8