From patchwork Thu Jun 1 09:43:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 100868 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp719124qge; Thu, 1 Jun 2017 02:45:57 -0700 (PDT) X-Received: by 10.200.51.27 with SMTP id t27mr643540qta.10.1496310357878; Thu, 01 Jun 2017 02:45:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496310357; cv=none; d=google.com; s=arc-20160816; b=m3drhwF1i+qeeFpbLH4MaXfPLgUypXnvcxYgBWY15atX5zmLaENUKFplUJuC9DoRJk oe0rywhA9Wx0eJHY6vrra5xBsBpB9lC2qGtGo0XxOOvqITGtZT7qS81+dbGY0Xq1QJD4 xaJ2wF6qXnk5HuyKXmFK58zE58Y/i93L67qEk67yxjCp34KJpOBAA7i6+5MC/CM+MF1l Nv4NXfitdiCiX4ZuR0f9cQGQA1STX8JS0Rpu0qOW7iEsnMs8c4KlakP2du1RH1/s1XEy WBnkrYBrBqEQ8LW+QwiIgUVn/kFZXPS7YPo4WA6MVLRUNpKnnRGP7o14rSU3pTejdc4F W4mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:delivered-to:arc-authentication-results; bh=gKgGwWAvSD4tKIasOq+5573Jk/8yoy8dRs5U5bw+RKA=; b=wVz3BBGxJsh0HseeLbHvxZaq61/A/ehY1PvGp0VXmocDVauPoql2B6d11BAeubF/Te PD973u0Te+36trN1cMglya5oUjX1NUHV5SOB9gZbX5eTHIxJJUYfOGzgrUhQsnMEk3yr I6GznWQEQq0Ja4txxFSsAEUNUZNMh4QON9/7idol5C73mPFDjfsCZpz7YrBneK0QcT7H IQtKbzm+jh+EPmzHoS/IqMn/yNP07pX5saks7IATPVDrGkKR9a/cWGd+dW8EbF8YeKI2 ppbLiw1pSeOrIsEDF3s/EIl7HcBhZKzrcY9j/bfj0QkB91PCQwlDuzOVJV9q6nMHRJAg f8Sg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id j66si18884775qkf.221.2017.06.01.02.45.57; Thu, 01 Jun 2017 02:45:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 82DD6609AA; Thu, 1 Jun 2017 09:45:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_SPAM, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id CA35E60BE9; Thu, 1 Jun 2017 09:44:49 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 19D0B609A7; Thu, 1 Jun 2017 09:44:37 +0000 (UTC) Received: from mail-wm0-f51.google.com (mail-wm0-f51.google.com [74.125.82.51]) by lists.linaro.org (Postfix) with ESMTPS id CCE6260A36 for ; Thu, 1 Jun 2017 09:44:09 +0000 (UTC) Received: by mail-wm0-f51.google.com with SMTP id n195so24325890wmg.1 for ; Thu, 01 Jun 2017 02:44:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=250GAiPPFP8TiMYbk1FLjjBY3w4NPzWs9yZ2GtkTSmQ=; b=S5pwrIKu7cDh50F2IzF2qYAos4pI609UkNfnKVHC9WzAfpxNJX7+aFWKl+H1OEIjkx X5BS5Yy7L4rwwUJg2gwES1v48kJ/1XDmOdsj2JnRGRj/4vtPEaXkI65mlXDM07r4u7Qe 00FworZ2uwak9kIOYdRSXmIfZCE1OUFSfusB2izdhzt/Aux5kpMXW18ON+OBPGyhJ132 SRV1SQ/uEImn/KjVZJ1vaiZRCsSENY4v7InWghcnjBNbMTXeYLAixD7pv7g1xKw2ucCV jUX0EaLHT9SnX8C95azogd98hXVOZ6GBZ5uIe+gT65kedvHY3nik9VQCGQ0bKO71VmKG y45Q== X-Gm-Message-State: AODbwcCu6cWfeD0gTae4nqOlD64hKk9xCaNugjtu5VtfF7DxzR4c9lb/ fSJ2QpFrfQPYzlE6cN7vWiN1 X-Received: by 10.28.182.195 with SMTP id g186mr7993785wmf.51.1496310248575; Thu, 01 Jun 2017 02:44:08 -0700 (PDT) Received: from localhost.localdomain ([196.71.200.86]) by smtp.gmail.com with ESMTPSA id 64sm23257679wmn.20.2017.06.01.02.44.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Jun 2017 02:44:07 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Thu, 1 Jun 2017 09:43:51 +0000 Message-Id: <20170601094353.16235-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170601094353.16235-1-ard.biesheuvel@linaro.org> References: <20170601094353.16235-1-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH 4/6] Platforms/AMD/Styx: enable SMMUs in the device tree X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space. This is not a problem for the onboard devices, but it would be useful if we could support arbitrary PCIe plug-in cards, even if they are only 32-bit DMA capable. Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table. While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 51 ++++++++++++++ Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 2 + Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 8293 -> 9357 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 72 +++++++++++++++++++- 4 files changed, 123 insertions(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index b18caf19985b..093db6517c1a 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -189,6 +190,46 @@ SetMacAddress ( #endif +STATIC +VOID +DisableSmmu ( + IN VOID *Fdt, + IN CONST CHAR8 *IommuPropName, + IN CONST CHAR8 *SmmuNodeName, + IN CONST CHAR8 *DeviceNodeName + ) +{ + INT32 Node; + INT32 Error; + + Node = fdt_path_offset (Fdt, DeviceNodeName); + if (Node <= 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n", + __FUNCTION__, DeviceNodeName, fdt_strerror (Node))); + return; + } + + Error = fdt_delprop (Fdt, Node, IommuPropName); + if (Error != 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to delete property %a: %a\n", + __FUNCTION__, IommuPropName, fdt_strerror (Error))); + return; + } + + Node = fdt_path_offset (Fdt, SmmuNodeName); + if (Node <= 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n", + __FUNCTION__, SmmuNodeName, fdt_strerror (Node))); + return; + } + + Error = fdt_del_node (Fdt, Node); + if (Error != 0) { + DEBUG ((DEBUG_WARN, "%a: Failed to delete node %a: %a\n", + __FUNCTION__, SmmuNodeName, fdt_strerror (Error))); + } +} + #define STYX_SOC_VERSION_MASK 0xFFF #define STYX_SOC_VERSION_A0 0x000 #define STYX_SOC_VERSION_B0 0x010 @@ -216,6 +257,16 @@ SetSocIdStatus ( #else SetDeviceStatus (Fdt, "kcs@e0010000", FALSE); #endif + + if (!PcdGetBool (PcdEnableSmmus)) { + DisableSmmu (Fdt, "iommu-map", "/smb/smmu@e0a00000", "/smb/pcie@f0000000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000"); +#if DO_XGBE + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0600000", "/smb/xgmac@e0700000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0800000", "/smb/xgmac@e0900000"); +#endif + } } STATIC diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index 8bb6e9fa41cb..fcf2f058fbdf 100644 --- a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -37,6 +37,7 @@ DxeServicesLib FdtLib MemoryAllocationLib + PcdLib PrintLib UefiBootServicesTableLib @@ -44,6 +45,7 @@ gAmdStyxTokenSpaceGuid.PcdSocCpuId gAmdStyxTokenSpaceGuid.PcdEthMacA gAmdStyxTokenSpaceGuid.PcdEthMacB + gAmdStyxTokenSpaceGuid.PcdEnableSmmus gArmTokenSpaceGuid.PcdSystemMemoryBase [FixedPcd] diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb index d380ea8714b85ec14f593b3795529c952e988df3..7ec1f63aff7805a3db7efc7a9b6e3c04f3c856cd 100644 GIT binary patch delta 2262 zcmcImOK1~O6rJ~?Z4;9;X;PDZG-^w!+G;FTi;6_STG84f{&qHwv4$pXX!=nUQt-bh zh(k6I)&frHm8YDF2%NCmn{Z95#=+#;Q{1^D*oct&T*#sZ$i$-Gfq#(9@%F^XG zfOkR6XB$2k6r#GqWl}h)y|DA2K_~*IHogRa|FaHdg|zkHHtNSvdqjy9JrlN(vYUPS}YwmQS65Ulhr_R z)D*MwK%RUyPrgDI7PN`GH0t!zmjwawjKZRVLeA=GU~h6&Qp#C^mL*&pji8m;06$f@ zJktiP$_*%`7p{d?&^OmiRU+>7M*313b}R3f?&-XLx=*`uPPlkOXNm{6@nDJf)|Z+? z`qyBI$&?<48C^qXzgxaIQmT``sM@na%K6mpDVH)hlJI;M;s+fpxsXZ_9SR2n;x)AdcbnOp=|iyfe^hu>wpQ)ux;gJ> z2SWzUZa>@EQ|+f(qZ=8upJ)*jp#1&hYej8?v7eC5o6o$qo8}CDh%jr#fw(d1rjAY7&Z^%7bP^Pzri!g5 zj(d3+9y}a*^w@9$E`isx#4Z zIGU)BclX75d;3#;X{{>WgMSiwERjfSN0QNcz2{i0H`d*!>4_e_E3Fy!G;Lb^)^55c Pqp1-`XuY64OMHI-={_7_ delta 1263 zcmcIj-%C?*6hGfv&8fTlVRO#SAInMjYiMF31Q{k`52X=QPujY>xwXw*+{!@9J@ppE z4*da{Jr$^}pohTMd@`Xx=w&@fM*0|xi0quZAB~~VO9#%q-*Z0aoX_{1@Av!Y!uGkg z5AyFl0FMd)0|1TJ>EA|bBejx}9FfWI!A`q-_58E}+l{wvo8*=lVw_|P-x*sZ*v5=; z>HtuyoE4k6Q#nW9K-EGmr*mpSnQRxcRd*%GqE_wIOBBFL22<5;T&upqxZUJ!FD;86*ymwKRCndPwk!H70MBjA0SGY_sh=%Cx40xMv;^4{?nRk_FPj(AIIs*3l$B z0_^Kp{!@_)5gAJRn(nFjF2oi#*dJrC_CfB_I8%-hN&LW3N3SIIao%x~{Y#E+Lpr2I zLx7i!cHDFLI>bKPlVK&EubrosEM$uu51+i`Ob^%HlDNvtdbG8cM4Jfh#c@|%{SbNi z7PIE}2#j9EB%$0bS7ogtWhO@FaK%+8p5S}erCj+DoN!(bN3XG_n?Q#=yjS8$Z@x+YkkNQFZpQ1)0afl}Zu{#N$=1&A6 KswRT50Q>; }; + sata0_smmu: smmu@e0200000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0200000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 332 4>, + <0 332 4>; + #iommu-cells = <2>; + dma-coherent; + }; + + sata1_smmu: smmu@e0c00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0c00000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 331 4>, + <0 331 4>; + #iommu-cells = <2>; + dma-coherent; + }; + sata@e0300000 { compatible = "snps,dwc-ahci"; reg = <0x0 0xe0300000 0x0 0xf0000>; interrupts = <0x0 0x163 0x4>; clocks = <0x2>; dma-coherent; + iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ }; sata@e0d00000 { @@ -137,6 +164,7 @@ interrupts = <0x0 0x162 0x4>; clocks = <0x2>; dma-coherent; + iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ }; i2c@e1000000 { @@ -257,6 +285,7 @@ #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; device_type = "pci"; bus-range = <0x0 0x7f>; msi-parent = <0x4>; @@ -283,6 +312,19 @@ <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ }; + pcie_smmu: smmu@e0a00000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0a00000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 333 4>, + <0 333 4>; + #iommu-cells = <1>; + dma-coherent; + }; + ccn@0xe8000000 { compatible = "arm,ccn-504"; reg = <0x0 0xe8000000 0x0 0x1000000>; @@ -382,6 +424,32 @@ phandle = <0xa>; }; + xgmac0_smmu: smmu@e0600000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0600000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 336 4>, + <0 336 4>; + #iommu-cells = <2>; + dma-coherent; + }; + + xgmac1_smmu: smmu@e0800000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0800000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 335 4>, + <0 335 4>; + #iommu-cells = <2>; + dma-coherent; + }; + xgmac@e0700000 { status = "disabled"; compatible = "amd,xgbe-seattle-v1a"; @@ -397,8 +465,8 @@ clock-names = "dma_clk", "ptp_clk"; phy-handle = <0x9>; phy-mode = "xgmii"; - #stream-id-cells = <0x18>; dma-coherent; + iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ linux,phandle = <0xb>; phandle = <0xb>; }; @@ -418,8 +486,8 @@ clock-names = "dma_clk", "ptp_clk"; phy-handle = <0xa>; phy-mode = "xgmii"; - #stream-id-cells = <0x18>; dma-coherent; + iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ linux,phandle = <0xc>; phandle = <0xc>; };