From patchwork Sat Apr 8 17:14:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 97051 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp744174qgd; Sat, 8 Apr 2017 10:15:15 -0700 (PDT) X-Received: by 10.200.54.13 with SMTP id m13mr44632221qtb.214.1491671715056; Sat, 08 Apr 2017 10:15:15 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id d13si8806914qkj.119.2017.04.08.10.15.14; Sat, 08 Apr 2017 10:15:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id BF9EF62C8F; Sat, 8 Apr 2017 17:15:10 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id AB60861C8F; Sat, 8 Apr 2017 17:15:08 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 0D868607A9; Sat, 8 Apr 2017 17:15:07 +0000 (UTC) Received: from mail-wm0-f49.google.com (mail-wm0-f49.google.com [74.125.82.49]) by lists.linaro.org (Postfix) with ESMTPS id CBDFB606A0 for ; Sat, 8 Apr 2017 17:15:04 +0000 (UTC) Received: by mail-wm0-f49.google.com with SMTP id u2so11420714wmu.0 for ; Sat, 08 Apr 2017 10:15:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aAPf4QGKQ414Sk1O4AyHO0aFYlfB4JnI4S6+pfD4d7o=; b=BlB9+utjeqPbxtSQnHI6ahfN82qIo4i+nkpZkpFlaV17AfBcfyeMjJxAFRQjy7rqXm ceymlPwi4cEedgJJg3YJEYzHbPfoKQQha0vXsPPiRAsg85F5eIIg6ZxoYBRj+ORV/d08 FidkKXXZd9proB6vFVRZvPD/KrLVbPoRpMUD8KFmZeGAa5Z5+W1b1GAYP2vRMZdHV/MN t0298m4NWB/iYkQn6OQnIxJsTbAnooTKftto27BiGWevI2pY17s2ljE2Ix6hrxg1nbl/ wgoIKgjtr/TU9HX90RG6GyHWEW3jdTE0KpJP4d6l8iYO4LIW0VtMoHGIMYyni/UbI+zM B92w== X-Gm-Message-State: AN3rC/4NPW9JdKaZoZqhcotZG4eUzvUgRCRYmKj3RdqwNfeL5RjunvcFMZQ+Qjwzsilw0eDEFls= X-Received: by 10.28.152.70 with SMTP id a67mr3869996wme.89.1491671703857; Sat, 08 Apr 2017 10:15:03 -0700 (PDT) Received: from localhost.localdomain ([196.81.139.226]) by smtp.gmail.com with ESMTPSA id n13sm3369155wmi.28.2017.04.08.10.15.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Apr 2017 10:15:03 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Sat, 8 Apr 2017 18:14:52 +0100 Message-Id: <20170408171453.13450-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170408171453.13450-1-ard.biesheuvel@linaro.org> References: <20170408171453.13450-1-ard.biesheuvel@linaro.org> Cc: alan@softiron.co.uk, lorenzo.pieralisi@arm.com Subject: [Linaro-uefi] [PATCH v2 1/2] Platforms/AMD: correct legacy PCI interrupt routing in DSDT X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The _PRT method in the PCI0 object describes something that resembles the legacy interrupt routing of the first slot only, but applies it to all PCI-PCI bridges, which means the wrong interrupt is reported for devices in slots 2 and 3. Since most devices support MSI, this is not actually a big deal, but it would be nice to fix this nonetheless. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Graeme Gregory --- Platforms/AMD/Styx/AcpiTables/Dsdt.asl | 63 +++++++++++--------- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl index 3bfa26acea07..4741bb487cc7 100644 --- a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl +++ b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl @@ -508,40 +508,45 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute - Name (_PRT, Package (0x04) // _PRT: PCI Routing Table + Name (_PRT, Package () // _PRT: PCI Routing Table { - Package (0x04) - { - 0xFFFF, - 0x00, - 0x00, - 0x0140 - }, + // INTA of the bridge device itself + Package () { 0x2FFFF, 0x0, 0x0, 0x140 } + }) - Package (0x04) + Device (EXP1) + { + Name (_ADR, 0x20001) // _ADR: Address + Name (_PRT, Package () // _PRT: PCI Routing Table { - 0xFFFF, - 0x01, - 0x00, - 0x0141 - }, - - Package (0x04) + Package () { 0xFFFF, 0x0, 0x0, 0x140 }, + Package () { 0xFFFF, 0x1, 0x0, 0x141 }, + Package () { 0xFFFF, 0x2, 0x0, 0x142 }, + Package () { 0xFFFF, 0x3, 0x0, 0x143 } + }) // _PRT + } + Device (EXP2) + { + Name (_ADR, 0x20002) // _ADR: Address + Name (_PRT, Package () // _PRT: PCI Routing Table { - 0xFFFF, - 0x02, - 0x00, - 0x0142 - }, - - Package (0x04) + Package () { 0xFFFF, 0x0, 0x0, 0x144 }, + Package () { 0xFFFF, 0x1, 0x0, 0x145 }, + Package () { 0xFFFF, 0x2, 0x0, 0x146 }, + Package () { 0xFFFF, 0x3, 0x0, 0x147 } + }) // _PRT + } + Device (EXP3) + { + Name (_ADR, 0x20003) // _ADR: Address + Name (_PRT, Package () // _PRT: PCI Routing Table { - 0xFFFF, - 0x03, - 0x00, - 0x0143 - } - }) // _PRT + Package () { 0xFFFF, 0x0, 0x0, 0x148 }, + Package () { 0xFFFF, 0x1, 0x0, 0x149 }, + Package () { 0xFFFF, 0x2, 0x0, 0x14A }, + Package () { 0xFFFF, 0x3, 0x0, 0x14B } + }) // _PRT + } Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings {