From patchwork Fri Apr 7 13:28:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 97023 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp285214qgd; Fri, 7 Apr 2017 06:29:09 -0700 (PDT) X-Received: by 10.55.156.2 with SMTP id f2mr25001779qke.61.1491571749011; Fri, 07 Apr 2017 06:29:09 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id f62si4805448qkj.205.2017.04.07.06.29.08; Fri, 07 Apr 2017 06:29:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9DF596366B; Fri, 7 Apr 2017 13:29:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 3C1AD6366B; Fri, 7 Apr 2017 13:29:04 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id DA36963A98; Fri, 7 Apr 2017 13:29:02 +0000 (UTC) Received: from mail-wr0-f170.google.com (mail-wr0-f170.google.com [209.85.128.170]) by lists.linaro.org (Postfix) with ESMTPS id F193363666 for ; Fri, 7 Apr 2017 13:29:01 +0000 (UTC) Received: by mail-wr0-f170.google.com with SMTP id t20so108093661wra.1 for ; Fri, 07 Apr 2017 06:29:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ZBPlvVxauoYXtNAbDWGi2kZwdkle56XVoP+Kp11/o8E=; b=YJbZAB1KxpnM93F4r0R965Ue91+HifShhlOCvOGSvucgRjZykuXBWlkbhhcF3NtAsz ddfKho/8NxTwdzTW/GYF4M4CibPVWc2RiRkY9EoLVrUaPV/eXsFCmSkcWpuq7lJGcY1l P8FmEa0HoxEfITtGTzyrmyQf+C80HlPffkbroTYOhQRusi1jFkzoGGLTgK6GA0MzqAHt qqHolcB9I6fnXTrSW6inneFPvnaCoYnlSJIlf4QMlVLmLZlSj8MUQRhJ8Ib5EA6ZOn5R 8EI+ERhJnrQbK8hgwGRbqwS8v/IvxR/o0jhdwtnhAitA2QOdpWr+6b7Qx4oHGrXxeNob YDww== X-Gm-Message-State: AFeK/H1BHnhNoTri+hetijQUVUs6eCwmN5dpz8qtcMEEwHcQflbpNhK/ XLgFOGbSmlisLKV8J8I= X-Received: by 10.28.220.132 with SMTP id t126mr18813796wmg.140.1491571740836; Fri, 07 Apr 2017 06:29:00 -0700 (PDT) Received: from localhost.localdomain ([196.81.139.226]) by smtp.gmail.com with ESMTPSA id c8sm5993936wrd.57.2017.04.07.06.28.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Apr 2017 06:28:59 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Fri, 7 Apr 2017 14:28:50 +0100 Message-Id: <20170407132851.28513-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 Cc: alan@softiron.co.uk Subject: [Linaro-uefi] [PATCH 1/2] Platforms/AMD: correct legacy PCI interrupt routing in DSDT X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The _PRT method in the PCI0 object describes something that resembles the legacy interrupt routing of the first slot only, but applies it to all PCI-PCI bridges, which means the wrong interrupt is reported for devices in slots 2 and 3. Since most devices support MSI, this is not actually a big deal, but it would be nice to fix this nonetheless. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Graeme Gregory --- Platforms/AMD/Styx/AcpiTables/Dsdt.asl | 52 +++++++------------- 1 file changed, 19 insertions(+), 33 deletions(-) diff --git a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl index 3bfa26acea07..49ef55fc7df6 100644 --- a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl +++ b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl @@ -508,39 +508,25 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute - Name (_PRT, Package (0x04) // _PRT: PCI Routing Table - { - Package (0x04) - { - 0xFFFF, - 0x00, - 0x00, - 0x0140 - }, - - Package (0x04) - { - 0xFFFF, - 0x01, - 0x00, - 0x0141 - }, - - Package (0x04) - { - 0xFFFF, - 0x02, - 0x00, - 0x0142 - }, - - Package (0x04) - { - 0xFFFF, - 0x03, - 0x00, - 0x0143 - } + Name (_PRT, Package () // _PRT: PCI Routing Table + { + // slot 1: dev 2 fn 1 + Package () { 0x20001, 0x0, 0x0, 0x140 }, + Package () { 0x20001, 0x1, 0x0, 0x141 }, + Package () { 0x20001, 0x2, 0x0, 0x142 }, + Package () { 0x20001, 0x3, 0x0, 0x143 }, + + // slot 2: dev 2 fn 2 + Package () { 0x20002, 0x0, 0x0, 0x144 }, + Package () { 0x20002, 0x1, 0x0, 0x145 }, + Package () { 0x20002, 0x2, 0x0, 0x146 }, + Package () { 0x20002, 0x3, 0x0, 0x147 }, + + // slot 3: dev 2 fn 3 + Package () { 0x20003, 0x0, 0x0, 0x148 }, + Package () { 0x20003, 0x1, 0x0, 0x149 }, + Package () { 0x20003, 0x2, 0x0, 0x14a }, + Package () { 0x20003, 0x3, 0x0, 0x14b } }) // _PRT Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings