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[54.225.227.206]) by mx.google.com with ESMTP id o142si7153494qke.72.2017.04.01.04.33.43; Sat, 01 Apr 2017 04:33:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id EFBFA60EA6; Sat, 1 Apr 2017 11:33:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 4C05462D68; Sat, 1 Apr 2017 11:33:27 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2338A60EA6; Sat, 1 Apr 2017 11:33:24 +0000 (UTC) Received: from mail-pg0-f54.google.com (mail-pg0-f54.google.com [74.125.83.54]) by lists.linaro.org (Postfix) with ESMTPS id A07E5608AC for ; Sat, 1 Apr 2017 11:33:16 +0000 (UTC) Received: by mail-pg0-f54.google.com with SMTP id 81so89639679pgh.2 for ; Sat, 01 Apr 2017 04:33:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KKgglHvsDmd+kAgl6YrGvVa5SFr11RKRpagx8lRsQnY=; b=UVJzFjk5KprGOgbkXe186YMuW0U9D6LUMqW/e0jW+z1qnuH/wDng8W49K728zw8igp UTJJzQ7X4/l1+SeQV3jWPAP/LvzHeQgOHYKpBgSWyQUidLRmPuEZcA2YioYnsqpWTWDi Ul5IWtT6F6tZ0IFCXIa3l6eA0ZQi7Ir5ReSl7FjZs/1PdNETivUSBpvkdgW159/Hr302 hTp6j9qjrC2HcrtxwtFB4quDyOwqCCF9dpZRyqbW2lpnMvvOtgPTneBHncQr+kld8AwG jwYnr3MWvt3GOqeAZneeKK7+JFXDG69hzD6FKnIkXSsd7DbsL9e+z4Nuj5ekIg1Qs727 FktQ== X-Gm-Message-State: AFeK/H1anU9DSI4hUM6z5Irki+j95VFlzF4p6GdGS1InsfGQTfuFjWILgksh4Tri9kI9TcI9cR0= X-Received: by 10.84.229.3 with SMTP id b3mr8752883plk.190.1491046395930; Sat, 01 Apr 2017 04:33:15 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm15704868pgc.60.2017.04.01.04.33.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 01 Apr 2017 04:33:15 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Sat, 1 Apr 2017 19:29:07 +0800 Message-Id: <1491046162-53797-3-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491046162-53797-1-git-send-email-chenhui.sun@linaro.org> References: <1491046162-53797-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , shaochangliang , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v2 02/17] Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue. X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The I350 Hilink state is not stable, so we need to modify the rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang Signed-off-by: Heyi Guo Signed-off-by: Yi Li Signed-off-by: Chenhui Sun --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 2 ++ Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 0b5a659..be02044 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -470,6 +470,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); Value |= (1 << 20); //bit 20: rxvalid enable RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \ + CH_RXTX_STATUS_CFG_EN|CH_RXTX_STATUS_CFG); } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9671c57..9a0f636 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -70,6 +70,10 @@ #define PCS_SDS_CFG_REG 0x204 #define SDS_CFG_STRIDE 0x4 +#define MUX_LOS_ALOS_REG_OFFSET 0x508 +#define MUX_CFG_STRIDE 0x4 +#define CH_RXTX_STATUS_CFG_EN BIT1 +#define CH_RXTX_STATUS_CFG BIT2 #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr))