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[54.225.227.206]) by mx.google.com with ESMTP id t28si17762871ioe.54.2017.03.20.06.15.39; Mon, 20 Mar 2017 06:15:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9506963E83; Mon, 20 Mar 2017 13:15:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 00C8263E88; Mon, 20 Mar 2017 13:15:12 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id F40BC63E7D; Mon, 20 Mar 2017 13:14:56 +0000 (UTC) Received: from mail-pg0-f49.google.com (mail-pg0-f49.google.com [74.125.83.49]) by lists.linaro.org (Postfix) with ESMTPS id 310BE63E74 for ; Mon, 20 Mar 2017 13:14:55 +0000 (UTC) Received: by mail-pg0-f49.google.com with SMTP id n190so77326894pga.0 for ; Mon, 20 Mar 2017 06:14:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pejj/z7kbi999QrOEihdGxqYHgivx28RjY4P4I2MW1g=; b=Joa+/JRgIpbxNweIi1Zk9ZsNXi3+fBXJHAni913uVdheTe+H+O05Grajt8yGYc+uYz aoIJc/UOdKVrFdw+WXu3UqqIdSOQbTNt6gVPdRGC3W7DIg2Eh/rPAGQyRuBECJG5zNj0 elcaqJoRqge3qALesrKMR0DYMN+oYyhsUV6VBXmqeOcVWIKXq5T/9dyLURzfSujgh21r NFdhtMCH04A53dYkGWHAtjs3V320BvPCNl9ZTM/OigJepfxz9BItL6mS471XuvRVlIDz 07xQ37V8//Z73Dcy4NHOwY9wUh6O/oFrLde+zZXsZhvMtEEEym/uIV58uNhjSOxKro2w PlkA== X-Gm-Message-State: AFeK/H2O3SlzgcEi2LKMSG7kdJXHt1ROIRXpHjzRsmo1z77Uu+p6IezVCoLuktpPvxOadueiF3iwag== X-Received: by 10.84.253.15 with SMTP id z15mr40573542pll.142.1490015694473; Mon, 20 Mar 2017 06:14:54 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.14.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:14:54 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:06 +0800 Message-Id: <1490015485-53685-3-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , shaochangliang , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 02/21] Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue. X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The I350 Hilink state is not stable, so we need to modify the rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 0b5a659..3bad240 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -23,6 +23,9 @@ #include #define PCIE_SYS_REG_OFFSET 0x1000 +#define MUX_LOS_ALOS_REG_OFFSET 0x508 +#define CH_RXTX_STATUS_CFG_EN BIT1 +#define CH_RXTX_STATUS_CFG BIT2 static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; @@ -470,6 +473,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); Value |= (1 << 20); //bit 20: rxvalid enable RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i*0x4, \ + CH_RXTX_STATUS_CFG_EN|CH_RXTX_STATUS_CFG); } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);