From patchwork Tue Feb 28 15:11:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 94636 Delivered-To: patch@linaro.org Received: by 10.140.20.113 with SMTP id 104csp1364460qgi; Tue, 28 Feb 2017 07:14:09 -0800 (PST) X-Received: by 10.200.38.72 with SMTP id v8mr3334095qtv.27.1488294849268; Tue, 28 Feb 2017 07:14:09 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id j135si1667082qke.129.2017.02.28.07.14.08; Tue, 28 Feb 2017 07:14:09 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id C37CB63706; Tue, 28 Feb 2017 15:14:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 1AE14636E5; Tue, 28 Feb 2017 15:12:37 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 7AEE8636DC; Tue, 28 Feb 2017 15:12:27 +0000 (UTC) Received: from mail-wm0-f49.google.com (mail-wm0-f49.google.com [74.125.82.49]) by lists.linaro.org (Postfix) with ESMTPS id 66065636DC for ; Tue, 28 Feb 2017 15:11:41 +0000 (UTC) Received: by mail-wm0-f49.google.com with SMTP id v77so14158220wmv.0 for ; Tue, 28 Feb 2017 07:11:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rYGZDOZm7tZQKVAqta8r3XRO8vkYBPURhkgBVGYHlr0=; b=UN/MvxVwdJrqAUveQGVEW9gd2FWZZHK/lxAE2fRBTXHgVIfZJvgKY4Nm4tK24CdUdy 57dId2wPu/1tVfQpxz1pHZwVTK0WLk951Y9z1eP7Kqzrxiy9tU+R9sUodZzeeUP5WFl6 sLWTQpTMxSwUTb44pLkWR3u0NOQsqji4Y1XnVx1EX1zBGoiFJLTIQPhT3KA1UBolRmhz MQhRw6vqEl8I7wPsXS1J4JfPRIak8w/oJ9lKw9Pbxy2aSjAcKrdvd47oDfwIxTv0PYV+ UWkVvXwk8dyjBC97QexrWLLs4Ew4MK54nzGSmJgxoIzIE6rcYNtmuRQ/qi0wyPWmMGxz ytMQ== X-Gm-Message-State: AMke39kGOyVqd7h8BbanAl+S+xLyDbz/xWLLUua8ShGXDOkrh+gC0RGZMDzp4wTmpwJxAPmIhdk= X-Received: by 10.28.144.135 with SMTP id s129mr2874143wmd.18.1488294700451; Tue, 28 Feb 2017 07:11:40 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id q1sm3086698wmd.6.2017.02.28.07.11.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 07:11:39 -0800 (PST) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, leif.lindholm@linaro.org, alan@softiron.co.uk Date: Tue, 28 Feb 2017 15:11:20 +0000 Message-Id: <1488294680-1884-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH v2 4/4] Platforms/AMD/Cello: enable strict memory permission policy X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Implement a strict separation between writable and executable memory, by enabling the new core features that - map PE/COFF code and data sections with either executable or writable permissions, but never both; - map all other regions with the XN attributes set. Note that the former requires 4 KB section alignment, which is not the default when using the tiny code model, so set the section alignment explicitly both for DEBUG and RELEASE builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index d7e1a538f863..cb8b6cd0d822 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -266,6 +266,9 @@ DEFINE DO_KCS = 0 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 +[BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1000 + ################################################################################ # # Pcd Section - list of all EDK II PCD Entries defined by this Platform @@ -430,6 +433,19 @@ DEFINE DO_KCS = 0 ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >= 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM and OS + # reserved ones, with the exception of LoaderData regions, of which OS loaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 + gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE