From patchwork Tue Feb 28 15:11:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 94633 Delivered-To: patch@linaro.org Received: by 10.140.20.113 with SMTP id 104csp1363474qgi; Tue, 28 Feb 2017 07:11:58 -0800 (PST) X-Received: by 10.237.60.41 with SMTP id t38mr3195719qte.148.1488294718132; Tue, 28 Feb 2017 07:11:58 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id s49si1659905qts.188.2017.02.28.07.11.57; Tue, 28 Feb 2017 07:11:58 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9EB9F636DF; Tue, 28 Feb 2017 15:11:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 6672D636E2; Tue, 28 Feb 2017 15:11:38 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 0CBD4636DC; Tue, 28 Feb 2017 15:11:36 +0000 (UTC) Received: from mail-wr0-f182.google.com (mail-wr0-f182.google.com [209.85.128.182]) by lists.linaro.org (Postfix) with ESMTPS id 6E7B1636DC for ; Tue, 28 Feb 2017 15:11:34 +0000 (UTC) Received: by mail-wr0-f182.google.com with SMTP id u108so10883842wrb.3 for ; Tue, 28 Feb 2017 07:11:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c0P2p64u6RO1vgls6qON6Hi7ExyzlbfPrgHNXvjkiZo=; b=YBxD67AXmgBEQQ10sB2CDf6VjKuHLY4tMGSFVLF7GppxZung19Ha6grZpH3hAJuwlu 0N8QP6QWsJihnrluS9XVqfol8Uy82EzU40qBze1OnPaWcMs8YQZd9gFPuWqmiqasD/2H burj66F5UBhBQChnZLLGJXRvOyHfChZXZPJSP5eGqy+osPxRPdgMKG8kdD92Uq7tcKBI UNwHn3PFN9fVyuSjvzKaI5SSQQT47v6qaKFhQvxPRSQT5OuVotI68iPfMK8yVqRq/Tz8 akBSuqv/01D/Byo2XIYy8FXMk7E8UITAzNsK4q15n3an3zydGoUf/a/wnSMEayZRc4rk hDWQ== X-Gm-Message-State: AMke39kJ5G/Fgd3x2DYzqqkm0B6QrJrULmCRKkomo1VqgCTIdAni4UgV5awsMFKZhII6T01Lecs= X-Received: by 10.223.135.43 with SMTP id a40mr2996442wra.197.1488294693547; Tue, 28 Feb 2017 07:11:33 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id q1sm3086698wmd.6.2017.02.28.07.11.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 07:11:32 -0800 (PST) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, leif.lindholm@linaro.org, alan@softiron.co.uk Date: Tue, 28 Feb 2017 15:11:17 +0000 Message-Id: <1488294680-1884-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH v2 1/4] Platforms/AMD/Styx/PlatformSmbiosDxe: don't write to string literals X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Remove the code from PlatformSmbiosDxe that writes to a string literal to turn the string 'L# Cache' into L1/L2/L3, and just emit the three versions instead. This is necessary given that string literals are emitted into .rodata by default, which makes them read-only when strict memory permissions are in effect. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index 5ee5d92fdf9c..7548be727849 100644 --- a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -354,17 +354,10 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7 = { CacheTypeUnknown, // System Cache Type CacheAssociativity2Way // Associativity }; -#if (FixedPcdGetBool (PcdIscpSupport)) -CHAR8 *mCacheInfoType7Strings[] = { - "L# Cache", - NULL -}; -#else CHAR8 *mCacheInfoType7Strings[] = { "Cache1", NULL }; -#endif /*********************************************************************** SMBIOS data definition TYPE9 System Slot Information @@ -710,7 +703,7 @@ CacheInfoUpdateSmbiosType7 ( dstType7.SocketDesignation = 1; // "L# Cache" // L1 cache settings - mCacheInfoType7Strings[0][1] = '1'; // "L# Cache" --> "L1 Cache" + mCacheInfoType7Strings[0] = "L1 Cache"; SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L1[0]; dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; @@ -726,7 +719,7 @@ CacheInfoUpdateSmbiosType7 ( LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); // L2 cache settings - mCacheInfoType7Strings[0][1] = '2'; // "L# Cache" --> "L2 Cache" + mCacheInfoType7Strings[0] = "L2 Cache"; SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L2[0]; dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; @@ -742,7 +735,7 @@ CacheInfoUpdateSmbiosType7 ( LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); // L3 cache settings - mCacheInfoType7Strings[0][1] = '3'; // "L# Cache" --> "L3 Cache" + mCacheInfoType7Strings[0] = "L3 Cache"; SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L3[0]; dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize;