From patchwork Wed Feb 15 14:54:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 94019 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp2064159qgi; Wed, 15 Feb 2017 06:55:58 -0800 (PST) X-Received: by 10.55.12.67 with SMTP id 64mr31482604qkm.171.1487170558504; Wed, 15 Feb 2017 06:55:58 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id f12si2993573qkf.134.2017.02.15.06.55.58; Wed, 15 Feb 2017 06:55:58 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2855060859; Wed, 15 Feb 2017 14:55:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 9A3A36074F; Wed, 15 Feb 2017 14:55:36 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 7100762D3B; Wed, 15 Feb 2017 14:55:29 +0000 (UTC) Received: from mail-pf0-f182.google.com (mail-pf0-f182.google.com [209.85.192.182]) by lists.linaro.org (Postfix) with ESMTPS id 9D89062D49 for ; Wed, 15 Feb 2017 14:55:15 +0000 (UTC) Received: by mail-pf0-f182.google.com with SMTP id 202so29090839pfx.2 for ; Wed, 15 Feb 2017 06:55:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dSOOyceurzfK4sG+rUSjQT+aGWadjbYgnKBpP4KvLHE=; b=aXI04jf61SuI12wkYcdvQNdIzbqSp3zG4c6FX3xGvc27tsypv2WHEAaygCBtnlNz3/ 1ZcWbE/TKoDnJv8gYjxIg/aTtpMQ+ZJOE7eMF9rMHLlEOLkUp8zBN6W19K5sPTal9b97 o3drbFRr8vCnOL3Ss/6eEC5nUNEXRzNMpvuBsXNwwvdsuFWols6eEhHx11d6hbs2aoUF gO52oARsap7F+RrSPIc0dXig/fsQn+MX7sRwdw1KitB+NdhB4IqCG+owtajUCwFbIYaN nizMsI5Mawy1mARVxCukEF5Stq1jMkAaM6meEVKL8+dYtCHBO0ZMAyIH3ZCTxXqSOSCR oN+Q== X-Gm-Message-State: AMke39n9ehvD2D/yiGkPrVPr9BRgg2g5itUPs8WhH5krqWJg13nTJokOWu9ZgNUDtTlB4DHMZSQ= X-Received: by 10.84.225.20 with SMTP id t20mr44432297plj.154.1487170514726; Wed, 15 Feb 2017 06:55:14 -0800 (PST) Received: from localhost.localdomain ([45.56.159.211]) by smtp.gmail.com with ESMTPSA id s24sm8212782pgo.25.2017.02.15.06.55.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 06:55:14 -0800 (PST) From: Haojian Zhuang To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Wed, 15 Feb 2017 22:54:57 +0800 Message-Id: <1487170499-22374-4-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487170499-22374-1-git-send-email-haojian.zhuang@linaro.org> References: <1487170499-22374-1-git-send-email-haojian.zhuang@linaro.org> Subject: [Linaro-uefi] [PATCH v4 3/5] Platforms/Hisilicon/HiKey: support all GPIO controller X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Enable all PL061 GPIO controllers on HiKey platform. Without this, only one PL061 GPIO controller could be supported on HiKey platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang Reviewed-by: Leif Lindholm --- .../Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c | 96 ++++++++++++++++++++++ .../Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf | 38 +++++++++ 2 files changed, 134 insertions(+) create mode 100644 Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c create mode 100644 Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf diff --git a/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c b/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c new file mode 100644 index 0000000..4a2943c --- /dev/null +++ b/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c @@ -0,0 +1,96 @@ +/** @file +* +* Copyright (c) 2015-2017, Linaro. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include + +#include + +#include + +#define GPIO0_CTRL_PIN_BASE (0 * PL061_GPIO_PINS) +#define GPIO1_CTRL_PIN_BASE (1 * PL061_GPIO_PINS) +#define GPIO2_CTRL_PIN_BASE (2 * PL061_GPIO_PINS) +#define GPIO3_CTRL_PIN_BASE (3 * PL061_GPIO_PINS) +#define GPIO4_CTRL_PIN_BASE (4 * PL061_GPIO_PINS) +#define GPIO5_CTRL_PIN_BASE (5 * PL061_GPIO_PINS) +#define GPIO6_CTRL_PIN_BASE (6 * PL061_GPIO_PINS) +#define GPIO7_CTRL_PIN_BASE (7 * PL061_GPIO_PINS) +#define GPIO8_CTRL_PIN_BASE (8 * PL061_GPIO_PINS) +#define GPIO9_CTRL_PIN_BASE (9 * PL061_GPIO_PINS) +#define GPIO10_CTRL_PIN_BASE (10 * PL061_GPIO_PINS) +#define GPIO11_CTRL_PIN_BASE (11 * PL061_GPIO_PINS) +#define GPIO12_CTRL_PIN_BASE (12 * PL061_GPIO_PINS) +#define GPIO13_CTRL_PIN_BASE (13 * PL061_GPIO_PINS) +#define GPIO14_CTRL_PIN_BASE (14 * PL061_GPIO_PINS) +#define GPIO15_CTRL_PIN_BASE (15 * PL061_GPIO_PINS) +#define GPIO16_CTRL_PIN_BASE (16 * PL061_GPIO_PINS) +#define GPIO17_CTRL_PIN_BASE (17 * PL061_GPIO_PINS) +#define GPIO18_CTRL_PIN_BASE (18 * PL061_GPIO_PINS) +#define GPIO19_CTRL_PIN_BASE (19 * PL061_GPIO_PINS) + +#define GPIO_CTRL_NUMS 20 +#define GPIO_PIN_NUMS (GPIO_CTRL_NUMS * PL061_GPIO_PINS) + +GPIO_CONTROLLER gGpioDevice[]= { + { GPIO0_CTRL_BASE, GPIO0_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO1_CTRL_BASE, GPIO1_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO2_CTRL_BASE, GPIO2_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO3_CTRL_BASE, GPIO3_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO4_CTRL_BASE, GPIO4_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO5_CTRL_BASE, GPIO5_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO6_CTRL_BASE, GPIO6_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO7_CTRL_BASE, GPIO7_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO8_CTRL_BASE, GPIO8_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO9_CTRL_BASE, GPIO9_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO10_CTRL_BASE, GPIO10_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO11_CTRL_BASE, GPIO11_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO12_CTRL_BASE, GPIO12_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO13_CTRL_BASE, GPIO13_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO14_CTRL_BASE, GPIO14_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO15_CTRL_BASE, GPIO15_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO16_CTRL_BASE, GPIO16_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO17_CTRL_BASE, GPIO17_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO18_CTRL_BASE, GPIO18_CTRL_PIN_BASE, PL061_GPIO_PINS }, + { GPIO19_CTRL_BASE, GPIO19_CTRL_PIN_BASE, PL061_GPIO_PINS }, +}; + +PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = { + GPIO_PIN_NUMS, GPIO_CTRL_NUMS, gGpioDevice +}; + +EFI_STATUS +EFIAPI +HiKeyGpioEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + // Install the Embedded Platform GPIO Protocol onto a new handle + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gPlatformGpioProtocolGuid, &gPlatformGpioDevice, + NULL + ); + if (EFI_ERROR (Status)) { + Status = EFI_OUT_OF_RESOURCES; + } + + return Status; +} diff --git a/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf b/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf new file mode 100644 index 0000000..d69c6f4 --- /dev/null +++ b/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf @@ -0,0 +1,38 @@ +# +# Copyright (c) 2015-2017, Linaro. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = HiKeyGpio + FILE_GUID = b51a851c-7bf7-463f-b261-cfb158b7f699 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKeyGpioEntryPoint + +[Sources.common] + HiKeyGpioDxe.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dec + +[LibraryClasses] + DebugLib + UefiDriverEntryPoint + +[Protocols] + gPlatformGpioProtocolGuid + +[Depex] + TRUE