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[54.225.227.206]) by mx.google.com with ESMTP id 37si7435431qtr.89.2017.02.13.07.10.52; Mon, 13 Feb 2017 07:10:52 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 65A9260860; Mon, 13 Feb 2017 15:10:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id E31A160868; Mon, 13 Feb 2017 15:10:38 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9314D608BB; Mon, 13 Feb 2017 15:10:34 +0000 (UTC) Received: from mail-ot0-f172.google.com (mail-ot0-f172.google.com [74.125.82.172]) by lists.linaro.org (Postfix) with ESMTPS id 919B56065A for ; Mon, 13 Feb 2017 15:10:33 +0000 (UTC) Received: by mail-ot0-f172.google.com with SMTP id f9so69440509otd.1 for ; Mon, 13 Feb 2017 07:10:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A70fyCa3eGGdaprovvjeA9hZ0/EgtGeVJ0n2DnPzK4o=; b=j73UYWDSOWVdH6S5ZXBoMF5iRvNybfg6+SVWN/XW/m+EyQRji1s+Tu0yb8uZq5wODG w3/ptqwHZRScDbAt8yrlkEcf+T5myeX7ikJX8UlyjHiI/2eQ7bdery8+CUIwbao4ezgE RHV61M29Q5esEUYBvDXJaiQyfCgE5owKOW18ptsdj8WEZ87VXjNWuz/Gd6f4aOd9GTq7 srEFu2ckFkszflCl00FaP7hziRqZQ/fjpKrZikgUm0+3aB26PtAYPZqCwtQVqXL4pxU9 hZlbr3VmpZvPH4RPDYurKSSvlcdof+56tsLn6lFqyqUBnxF5iqyhK4bGHA7A0zzJm3fJ sWNw== X-Gm-Message-State: AMke39kMFvZLY+U4x0UJJxAfkmZ0djKDOxAKAQ3hXlwwKGRYU15+LIfDcVOWzddPUvUoeu6I8f4= X-Received: by 10.99.0.196 with SMTP id 187mr27558490pga.139.1486998633034; Mon, 13 Feb 2017 07:10:33 -0800 (PST) Received: from localhost.localdomain ([45.56.159.191]) by smtp.gmail.com with ESMTPSA id z70sm21666857pff.26.2017.02.13.07.10.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 13 Feb 2017 07:10:32 -0800 (PST) From: Haojian Zhuang To: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 13 Feb 2017 23:10:17 +0800 Message-Id: <1486998621-30420-2-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486998621-30420-1-git-send-email-haojian.zhuang@linaro.org> References: <1486998621-30420-1-git-send-email-haojian.zhuang@linaro.org> Subject: [Linaro-uefi] [PATCH v3 1/5] Platforms/Hisilicon/HiKey: append more register definitions X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Add more register definitions in Hi6220 SoC. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Hi6220/Include/Hi6220.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Chips/Hisilicon/Hi6220/Include/Hi6220.h b/Chips/Hisilicon/Hi6220/Include/Hi6220.h index 203424a..6b87524 100644 --- a/Chips/Hisilicon/Hi6220/Include/Hi6220.h +++ b/Chips/Hisilicon/Hi6220/Include/Hi6220.h @@ -48,15 +48,41 @@ #define SC_PERIPH_CLKDIS0 0x204 #define SC_PERIPH_CLKSTAT0 0x208 +#define SC_PERIPH_CLKEN3 0x230 #define SC_PERIPH_RSTEN0 0x300 #define SC_PERIPH_RSTDIS0 0x304 #define SC_PERIPH_RSTSTAT0 0x308 +#define SC_PERIPH_RSTEN3 0x330 +#define SC_PERIPH_RSTDIS3 0x334 +#define SC_PERIPH_RSTSTAT3 0x338 #define RST0_USBOTG_BUS BIT4 #define RST0_POR_PICOPHY BIT5 #define RST0_USBOTG BIT6 #define RST0_USBOTG_32K BIT7 +/* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */ +#define PERIPH_RST0_MMC2 (1 << 2) + +/* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */ +#define PERIPH_RST3_CSSYS (1 << 0) +#define PERIPH_RST3_I2C0 (1 << 1) +#define PERIPH_RST3_I2C1 (1 << 2) +#define PERIPH_RST3_I2C2 (1 << 3) +#define PERIPH_RST3_I2C3 (1 << 4) +#define PERIPH_RST3_UART1 (1 << 5) +#define PERIPH_RST3_UART2 (1 << 6) +#define PERIPH_RST3_UART3 (1 << 7) +#define PERIPH_RST3_UART4 (1 << 8) +#define PERIPH_RST3_SSP (1 << 9) +#define PERIPH_RST3_PWM (1 << 10) +#define PERIPH_RST3_BLPWM (1 << 11) +#define PERIPH_RST3_TSENSOR (1 << 12) +#define PERIPH_RST3_DAPB (1 << 18) +#define PERIPH_RST3_HKADC (1 << 19) +#define PERIPH_RST3_CODEC_SSI (1 << 20) +#define PERIPH_RST3_PMUSSI1 (1 << 22) + #define EYE_PATTERN_PARA 0x7053348c #define MDDRC_AXI_BASE 0xF7120000 @@ -74,4 +100,7 @@ #define PMUSSI_BASE 0xF8000000 +#define PMUSSI_REG(x) (PMUSSI_BASE + ((x) << 2)) + + #endif /* __HI6220_H__ */