From patchwork Wed Dec 7 11:49:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 87073 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp281617qgi; Wed, 7 Dec 2016 04:14:31 -0800 (PST) X-Received: by 10.55.174.135 with SMTP id x129mr64469605qke.133.1481112871059; Wed, 07 Dec 2016 04:14:31 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id p11si14274102qkh.230.2016.12.07.04.14.30; Wed, 07 Dec 2016 04:14:31 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id EE17960E59; Wed, 7 Dec 2016 12:14:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id F30866097E; Wed, 7 Dec 2016 11:59:04 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id A02AF60E94; Wed, 7 Dec 2016 11:58:35 +0000 (UTC) Received: from mail-pf0-f177.google.com (mail-pf0-f177.google.com [209.85.192.177]) by lists.linaro.org (Postfix) with ESMTPS id 1C28A62D9A for ; Wed, 7 Dec 2016 11:52:53 +0000 (UTC) Received: by mail-pf0-f177.google.com with SMTP id i88so76836397pfk.2 for ; Wed, 07 Dec 2016 03:52:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ahsWuFXXtRUGVADpxXg/vS9jlPYMLvvF+1ek15qIKcs=; b=SR746DelrKqiXJNuFmDM7jQGAgOABioJNvZf0Qgxbsz0fwijz69gJ8wT4Ofz7RgMI2 H/MO4ZN+D+bQ7oKgMMdXtP1TKx0WIJJIDGnFBZPTvwoicwXw/zIsTZ/98IaHPUX+oPlj pHvH9pAM7BvhlY8zTfVxb1j5QcgHAv/EEKtB9NJFUGQmCURodJOVFqnjPwdgk2UQ55A4 YuimFLAP+GQYhcwnvaZS1xVUhauJrbHCzM2YXQwgw6xvPn+QegsPlgQRjShkA/67Llrx 9lJ2OrsxlSi8nHKt9zf2GmEH5fbcFuYbL8S6fv3Cr2a9a7hXGQ2VJ151MCfm08WkSQGu C9jg== X-Gm-Message-State: AKaTC028JnVsI36HTBmvK87i7Jb3Vdnq9pJg799vLSkvehKPM81qFM7kpdR4hqLlghFJR9+A3Fo= X-Received: by 10.84.193.129 with SMTP id f1mr146425892pld.129.1481111572359; Wed, 07 Dec 2016 03:52:52 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id y20sm42169141pfj.26.2016.12.07.03.52.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Dec 2016 03:52:51 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Wed, 7 Dec 2016 19:49:34 +0800 Message-Id: <1481111375-71058-38-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481111375-71058-1-git-send-email-heyi.guo@linaro.org> References: <1481111375-71058-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v7 37/38] Platforms/D05/ACPI: dynamically detect chip version to set port enable/disable X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The pcie device should be disable for chip's reason before EC and the pcie device should be enable after EC for OS. EC: Engineering change, silicon minor upgrade. Enable all the pcie device, because it is ok for bios. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Graeme Gregory Reviewed-by: Leif Lindholm --- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 33 ++++++++++++++++++---- Platforms/Hisilicon/D05/D05.dsc | 3 +- 2 files changed, 29 insertions(+), 7 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 8574648..f9b4722 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -19,6 +19,27 @@ //#include "ArmPlatform.h" Scope(_SB) { + /* 0xD000E014:Hi1616 chip version reg[19:8], 0x102-after EC, 0x101/0-before EC. */ + OperationRegion (ECRA, SystemMemory, 0xD000E014, 0x4) + Field (ECRA, AnyAcc, NoLock, Preserve) + { + VECA, 32, + } + + /* RBYV:Return by chip version + * the pcie device should be disable for chip's reason before EC, + * and the pcie device should be enable after EC for OS */ + Method (RBYV) + { + Store(VECA, local0) + And (local0, 0xFFF00, local1) + If (LEqual (local1, 0x10200)) { + Return (0xf) + } Else { + Return (0x0) + } + } + // 1P NA PCIe2 Device (PCI2) { @@ -147,7 +168,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI4) @@ -220,7 +241,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI5) @@ -292,7 +313,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI6) // 1P NB PCIe3 @@ -363,7 +384,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI7) // 2P NA PCIe2 @@ -505,7 +526,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCIc) @@ -577,7 +598,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCId) } diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 3242b29..1f5e084 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -167,7 +167,8 @@ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + ## enable all the pcie device, because it is ok for bios + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 ## SP805 Watchdog - Motherboard Watchdog