From patchwork Wed Dec 7 11:49:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 87040 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp273703qgi; Wed, 7 Dec 2016 03:58:53 -0800 (PST) X-Received: by 10.200.49.235 with SMTP id i40mr66620329qte.170.1481111933585; Wed, 07 Dec 2016 03:58:53 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id 31si14249711qts.115.2016.12.07.03.58.53; Wed, 07 Dec 2016 03:58:53 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 4205163666; Wed, 7 Dec 2016 11:58:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id B01BA60ECF; Wed, 7 Dec 2016 11:53:23 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E988060E98; Wed, 7 Dec 2016 11:53:10 +0000 (UTC) Received: from mail-pf0-f178.google.com (mail-pf0-f178.google.com [209.85.192.178]) by lists.linaro.org (Postfix) with ESMTPS id 5746E60E98 for ; Wed, 7 Dec 2016 11:51:54 +0000 (UTC) Received: by mail-pf0-f178.google.com with SMTP id c4so77216227pfb.1 for ; Wed, 07 Dec 2016 03:51:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qDfdJfeTO5UH59xX+Xf4+MqohpdnM/JA4uOpbAT1Xp4=; b=kpmIhnWaCk1Hz65UU0p7QgjFDokyYexGfvPrqETAvccAp4Ycu6O2ehogqUqJz4xQGi uLj/R8fTSDON/9DU0Xh4wlYwke/H9B3P24JQQXpioIZxS2KoCHJ6jhQeQSKRWLyG2Y2U vFy5RMGn8kvQELdhZ8GYs7gUgoBHoRM6caDImcP0Dj8E+/NwpVO4Ow517K0oR6DFunBk O2Y0JeTqqAWHf8kwRJ2+QrP5cH2RpWkxLUUdnQVicpeD0FRnIaGrIpmSjCkUVTpGIzBV 4ETNDre+7CIqqvtfeb4QEFrdrHZ4uTCSqxU9hE7o31nyvpSdlTXx8Nq4pJ6Wr/+ambHX l2+g== X-Gm-Message-State: AKaTC03recgWN1sQXYjiJg2X84quAGdLUisSDNflXe9U+fj8G9SuOIIAOxBOJUjFpHbQemA9ZNQ= X-Received: by 10.99.208.21 with SMTP id z21mr120361909pgf.79.1481111513658; Wed, 07 Dec 2016 03:51:53 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id y20sm42169141pfj.26.2016.12.07.03.51.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Dec 2016 03:51:53 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Wed, 7 Dec 2016 19:49:06 +0800 Message-Id: <1481111375-71058-10-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481111375-71058-1-git-send-email-heyi.guo@linaro.org> References: <1481111375-71058-1-git-send-email-heyi.guo@linaro.org> Cc: sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v7 09/38] D02/D03/D05: Support Spd mirror mode X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Add Spd mirror mode related registers definition, this is used by memoryinit binary code,base this definition it could support spd mirror mode to have diffrent configuration about MR register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index c24930f..2663cad 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ UINT16 DimmSize; UINT16 DimmSpeed; UINT32 RankSize; + UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode struct DDR_RANK Rank[MAX_RANK_DIMM]; }DDR_DIMM; @@ -337,6 +338,7 @@ typedef struct _MEMORY{ UINT8 Config0; UINT8 marginTest; UINT8 Config1[5]; + UINT8 ErrorBypass; //register of spd mirror mode UINT32 Config2; }MEMORY; @@ -789,6 +791,8 @@ struct ODT_ACTIVE_STRUCT { #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM #define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte