From patchwork Tue Dec 6 10:57:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 86782 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp1961744qgi; Tue, 6 Dec 2016 03:20:30 -0800 (PST) X-Received: by 10.200.53.99 with SMTP id z32mr60095483qtb.194.1481023230901; Tue, 06 Dec 2016 03:20:30 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id d20si11416011qtd.301.2016.12.06.03.20.30; Tue, 06 Dec 2016 03:20:30 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 92B75609D7; Tue, 6 Dec 2016 11:20:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id DE3B9636AD; Tue, 6 Dec 2016 11:05:22 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2465860E99; Tue, 6 Dec 2016 11:04:46 +0000 (UTC) Received: from mail-pf0-f175.google.com (mail-pf0-f175.google.com [209.85.192.175]) by lists.linaro.org (Postfix) with ESMTPS id 8C5C660E99 for ; Tue, 6 Dec 2016 11:00:19 +0000 (UTC) Received: by mail-pf0-f175.google.com with SMTP id i88so69907441pfk.2 for ; Tue, 06 Dec 2016 03:00:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Q43LorIqZ0IHVVpbqZozJTOKujUCanjxfMbeuIPtI10=; b=m1+ZZ08hLkBEgSQh8G2eGqwmsGA8NOuyleBoTzsKohvunhVnUgyXL3DGjtwqyZrVUQ FbJPjVjiZ5sbE71KcctrXTJDYXZLYpvKFSdj5IsAWAXe+CfdXEL7RAE+JZgXcQOlE0b3 UdTY2N7Z1aGo2KHIaGRdnz1qIUogYKhszuq0WdsfIXdwn9cYK5tCiXVfnSzPqh/Hbc51 ZHRBloTEG16VP+pxjUhDLEXBIl9KOfnzk1MEnkNONXmLFyRH6BG+doPBTuOxqKHfcJL3 LhwFjsspIMu48DU/moQJvwXUv5DBm7Q8HmU9VciW7PhQlGBfPw6YSMIJCx0QytoEUyca tTKQ== X-Gm-Message-State: AKaTC037x5/tahQ/3w7E0anvdz8ayp13si8HmrqoelvqR1fQy+zz7CuNqNwvHh6+aloaJQBtmys= X-Received: by 10.84.136.75 with SMTP id 69mr132943707plk.52.1481022018855; Tue, 06 Dec 2016 03:00:18 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id x26sm6980952pge.24.2016.12.06.03.00.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Dec 2016 03:00:18 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 6 Dec 2016 18:57:07 +0800 Message-Id: <1481021828-59826-37-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481021828-59826-1-git-send-email-heyi.guo@linaro.org> References: <1481021828-59826-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v6 36/37] Platforms/D05/ACPI:dynamically detect chip version to set port enable/disable X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The pcie device should be disable for chip's reason before EC and the pcie device should be enable after EC for OS. Enable all the pcie device, because it is ok for bios. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 33 ++++++++++++++++++---- Platforms/Hisilicon/D05/D05.dsc | 3 +- 2 files changed, 29 insertions(+), 7 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 8574648..f9b4722 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -19,6 +19,27 @@ //#include "ArmPlatform.h" Scope(_SB) { + /* 0xD000E014:Hi1616 chip version reg[19:8], 0x102-after EC, 0x101/0-before EC. */ + OperationRegion (ECRA, SystemMemory, 0xD000E014, 0x4) + Field (ECRA, AnyAcc, NoLock, Preserve) + { + VECA, 32, + } + + /* RBYV:Return by chip version + * the pcie device should be disable for chip's reason before EC, + * and the pcie device should be enable after EC for OS */ + Method (RBYV) + { + Store(VECA, local0) + And (local0, 0xFFF00, local1) + If (LEqual (local1, 0x10200)) { + Return (0xf) + } Else { + Return (0x0) + } + } + // 1P NA PCIe2 Device (PCI2) { @@ -147,7 +168,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI4) @@ -220,7 +241,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI5) @@ -292,7 +313,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI6) // 1P NB PCIe3 @@ -363,7 +384,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCI7) // 2P NA PCIe2 @@ -505,7 +526,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCIc) @@ -577,7 +598,7 @@ Scope(_SB) } Method (_STA, 0x0, NotSerialized) { - Return (0x0) + Return (RBYV()) } } // Device(PCId) } diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 3242b29..1f5e084 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -167,7 +167,8 @@ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + ## enable all the pcie device, because it is ok for bios + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 ## SP805 Watchdog - Motherboard Watchdog