From patchwork Fri Dec 2 04:12:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 86195 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp84228qgi; Thu, 1 Dec 2016 20:16:24 -0800 (PST) X-Received: by 10.55.3.67 with SMTP id 64mr41603023qkd.257.1480652184638; Thu, 01 Dec 2016 20:16:24 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id a16si2000408qtb.121.2016.12.01.20.16.23; Thu, 01 Dec 2016 20:16:24 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 7D0ED62F36; Fri, 2 Dec 2016 04:16:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id CF33760F2E; Fri, 2 Dec 2016 04:15:09 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id C934260EDE; Fri, 2 Dec 2016 04:15:02 +0000 (UTC) Received: from mail-pg0-f41.google.com (mail-pg0-f41.google.com [74.125.83.41]) by lists.linaro.org (Postfix) with ESMTPS id 3D5D660E8A for ; Fri, 2 Dec 2016 04:15:01 +0000 (UTC) Received: by mail-pg0-f41.google.com with SMTP id 3so102739089pgd.0 for ; Thu, 01 Dec 2016 20:15:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0/nNF7SlluIcoWkn2ZdYOHCeUMVp4HjjKJ8Y0mlicPI=; b=KlQUfDc9OgERgJXxyxZafCbrsjrq8w+YAueWzIO32tyLBXvFjOQgh/RFPBNFALzj7L Kv/zcr0EOmPZyJmrJFLTZJg3VQ4+XSNbBBQDAz1lCULLxNEdPLLhqB6tA0HFcNGh+pf1 9klMuX4mUfmRI9uhQkYnkFV1E3nNuAdUb23BVKkXbHoRfg/o20C/CDHwdOZPXiBOhXh6 R0doFMzxkf7DFhrmYrQpwytnuJ4VW+Gvpy4sljgtoCKDrzSvbxO6jCQD5nLLP46MrO52 fVkCI6yTBNOaqSfeeXlFJCWOHLGExguAixoilTU4UEtHB6NFSdxu2/NPqkXiBor6cuuI L05A== X-Gm-Message-State: AKaTC01/8nYXuATyrf+Nove9xehHwd0bweW0T+na8qcemQiyY76jcm84U5NjDX6iwN/T7t+Abeg= X-Received: by 10.98.220.157 with SMTP id c29mr42436228pfl.29.1480652100560; Thu, 01 Dec 2016 20:15:00 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id u78sm3402349pfa.53.2016.12.01.20.14.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Dec 2016 20:15:00 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Fri, 2 Dec 2016 12:12:55 +0800 Message-Id: <1480652017-31676-3-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480652017-31676-1-git-send-email-heyi.guo@linaro.org> References: <1480652017-31676-1-git-send-email-heyi.guo@linaro.org> Cc: sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v5 02/44] Hisilicon/HwMemInitLib.h: fix typo for phyDqsFallRiseDelay X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" phyDqsFallRiseDelay was spelt as phyDqs*Fail*RiseDelay; just fix the typo,also update the related binaries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- .../PlatformSysCtrlLibHi1610.lib | Bin 273980 -> 305230 bytes .../Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib | Bin 439708 -> 431524 bytes Chips/Hisilicon/Include/Library/HwMemInitLib.h | 2 +- .../Binary/D02/MemoryInitPei/MemoryInit.efi | Bin 159136 -> 160672 bytes .../Binary/D03/MemoryInitPei/MemoryInit.efi | Bin 158944 -> 161280 bytes 5 files changed, 1 insertion(+), 1 deletion(-) diff --git a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi index ce63a5c..8d2a9f3 100644 Binary files a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi and b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi differ diff --git a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi index cf6bb92..f335e5c 100644 Binary files a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi and b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi differ diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib index 1d9f248..ca78ae6 100644 Binary files a/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib and b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib differ diff --git a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib index 6e9c41d..5f8ab73 100644 Binary files a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib and b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib differ diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 6bf323d..c24930f 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -254,7 +254,7 @@ typedef struct _DDR_Channel{ UINT8 per_cs_training_en; UINT32 phyRdDataEnIeDly; UINT32 phyPadCalConfig; - UINT32 phyDqsFailRiseDelay; + UINT32 phyDqsFallRiseDelay; UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency;