From patchwork Sat Nov 19 08:37:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 83069 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp501051qge; Sat, 19 Nov 2016 00:45:21 -0800 (PST) X-Received: by 10.55.49.203 with SMTP id x194mr5316170qkx.93.1479545121472; Sat, 19 Nov 2016 00:45:21 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id a8si3559988qte.122.2016.11.19.00.45.21; Sat, 19 Nov 2016 00:45:21 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 1CD66634FE; Sat, 19 Nov 2016 08:45:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 0E96D60CDB; Sat, 19 Nov 2016 08:41:20 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 941A460CDB; Sat, 19 Nov 2016 08:41:15 +0000 (UTC) Received: from mail-pg0-f44.google.com (mail-pg0-f44.google.com [74.125.83.44]) by lists.linaro.org (Postfix) with ESMTPS id EEFF560CDB for ; Sat, 19 Nov 2016 08:39:34 +0000 (UTC) Received: by mail-pg0-f44.google.com with SMTP id p66so111353331pga.2 for ; Sat, 19 Nov 2016 00:39:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qDD0hs9wn0nurokoI9DNIDACuNwAmcceqKeJtuxwcTE=; b=Y5iyP34KvoJ6G6lQ+Q0uTCI6tbbiZa8RfyJOI9TvsQbU3rQkenA+QQ8z7n8lY9Zo1B QyhiYM5Rsziq12h6q0ZT66EQrXcv8oLqeABoDI6f310dCb7BwQ2k9ML9CluMArijX22W R6L30RB7gkC9uMfD1V9b3zJ9rzAOBkn3BsHervZnMxCux+8MZpYQA+juPHO/VFqKeabn oFY0VWM3JqqAPHT6eJlUcJ/s39Xyq9hRJt8WPCr35v0HEd7fh7kVQ4Gs16BIt+prqasb Xayov1rKnKpM+GveDo0eh3L0dUhxmWsHWaO09YHxgESWmIMEQ66HZTPH4X14lhC+E965 0+rQ== X-Gm-Message-State: AKaTC02GX8OOorlmCkmaxMbDbMDrdJu8HEe5907/J0NtS2fhqLGj1u1p1iDdrYZQNKIV7z7Cvdk= X-Received: by 10.98.100.66 with SMTP id y63mr5002985pfb.49.1479544774288; Sat, 19 Nov 2016 00:39:34 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id v193sm5106241pgb.37.2016.11.19.00.39.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 19 Nov 2016 00:39:33 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Sat, 19 Nov 2016 16:37:22 +0800 Message-Id: <1479544691-59575-8-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> References: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [Patch v4 07/56] Hisilicon/PCIeInit: fix PciePcsInit bug X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" There are 8 phys at each Pcie Controller, so it should be set for 8 times loop. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 8 +++++--- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 ++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index bd871d6..0b5a659 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -466,9 +466,11 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) UINT32 Value = 0; if (0x1610 == soctype) { - RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); - Value |= (1 << 20); - RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); + for (i = 0; i < PcieMaxLanNum; i++) { + RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + Value |= (1 << 20); //bit 20: rxvalid enable + RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); } diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 1e8db97..9671c57 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -68,6 +68,8 @@ #define PCIE_BAR_TYPE_64 (2) #define PCIE_BAR_PREFETCH_MODE (1) +#define PCS_SDS_CFG_REG 0x204 +#define SDS_CFG_STRIDE 0x4 #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr))