From patchwork Sat Nov 19 08:37:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 83068 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp500935qge; Sat, 19 Nov 2016 00:44:53 -0800 (PST) X-Received: by 10.107.189.196 with SMTP id n187mr3663598iof.88.1479545093688; Sat, 19 Nov 2016 00:44:53 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id j62si4455803itg.72.2016.11.19.00.44.53; Sat, 19 Nov 2016 00:44:53 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3649F60CF6; Sat, 19 Nov 2016 08:44:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id C6A8A62FCA; Sat, 19 Nov 2016 08:41:08 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8EBCD62FAF; Sat, 19 Nov 2016 08:41:02 +0000 (UTC) Received: from mail-pg0-f49.google.com (mail-pg0-f49.google.com [74.125.83.49]) by lists.linaro.org (Postfix) with ESMTPS id 343ED60CD6 for ; Sat, 19 Nov 2016 08:39:33 +0000 (UTC) Received: by mail-pg0-f49.google.com with SMTP id 3so111497233pgd.0 for ; Sat, 19 Nov 2016 00:39:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uTplkmaCPwpK9DSvnZGYwdJQPAJSU+iblup69Fimang=; b=IOSXAH0o2R3JRps+lfF/dR4/08EnWFOj2QxrqXFBD6zJa731l5bpPuSE3slvFDrYIw hAwlqR/wsy1wI3Dk3O/ugGG/LXIjJV+taVpr6SJ3IlzZtxMCmXfTJwFp0e42BEfQSB7U pGGClDzVohmO/+Rg5f82ugowe4kLxqby/aG+j26q/vmnp69UMldDiopR0rcvMutVxRuK J1/sBVFFaB9XbRYwHxROSWnkIITGRG0XFWdJ2E8OyV6jtX8aSSJOuc6rRvPEVkZNerJ6 3yAECweOWTpLKFIYpmt+qBfNb+sfTLxqK3e2MfVZ0AumoQ1L211a64fmpJgo5DGV7Y34 kRKg== X-Gm-Message-State: AKaTC01uyf77U0AtBeuglZXM+jjIhq4w4C+2B8igtBmw3UEXCFj/b5r3x5TMW9+ZgOCv7Ja02OU= X-Received: by 10.99.124.20 with SMTP id x20mr8513045pgc.60.1479544772560; Sat, 19 Nov 2016 00:39:32 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id v193sm5106241pgb.37.2016.11.19.00.39.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 19 Nov 2016 00:39:32 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Sat, 19 Nov 2016 16:37:21 +0800 Message-Id: <1479544691-59575-7-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> References: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [Patch v4 06/56] Hisilicon/PCIeInit: Remove unused function PciePortReset X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The PciePortReset function is unused, so we remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 38 ---------------------- 1 file changed, 38 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 399155c..bd871d6 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -573,44 +573,6 @@ VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) } -EFI_STATUS PciePortReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - if(Port >= PCIE_MAX_PORT_NUM) - { - return EFI_INVALID_PARAMETER; - } - - - if(PcieIsLinkUp(soctype, HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port]) - { - (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port); - } - - mPcieIntCfg.PortIsInitilized[Port] = FALSE; - mPcieIntCfg.DmaResource[Port] = (VOID *)NULL; - mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0; - mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0; - ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U)); - - if(Port <= 2) - { - RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1); - MicroSecondDelay(0x1000); - - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1); - MicroSecondDelay(0x1000); - } - else - { - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1); - MicroSecondDelay(0x1000); - - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1); - MicroSecondDelay(0x1000); - } - return EFI_SUCCESS; -} - EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { UINT32 PortIndexInSicl;