From patchwork Sat Nov 19 08:37:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 83066 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp500645qge; Sat, 19 Nov 2016 00:43:42 -0800 (PST) X-Received: by 10.200.54.244 with SMTP id b49mr2434627qtc.93.1479545022232; Sat, 19 Nov 2016 00:43:42 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id f27si3549674qta.264.2016.11.19.00.43.42; Sat, 19 Nov 2016 00:43:42 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E280A60D10; Sat, 19 Nov 2016 08:43:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 367DB60C91; Sat, 19 Nov 2016 08:40:35 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2690760D3E; Sat, 19 Nov 2016 08:40:31 +0000 (UTC) Received: from mail-pg0-f53.google.com (mail-pg0-f53.google.com [74.125.83.53]) by lists.linaro.org (Postfix) with ESMTPS id A452660C89 for ; Sat, 19 Nov 2016 08:39:29 +0000 (UTC) Received: by mail-pg0-f53.google.com with SMTP id 3so111496887pgd.0 for ; Sat, 19 Nov 2016 00:39:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/oHQ36nOvx/asXqnuDJ9WBpc/M5B1fe10lhyBSkCz+E=; b=OVQdho6/i2EE8RteGtpyqaTLe7v203qrjtylvc5faYgs2kjWIitN2GZE0FBE1Gn1rx sh6ZqMjenMfrke0UYf+4i+efltWEyMxJYs5tKTviJNh34Vd641RdXa0+now2O1aKtgH+ OCXdk62O01d9rw3n6lDmXhWS43pbawdRyg+ptwiz4sX8Y+fIsrlpnF5pM6cP/ujYHZbF EH3F12fu9HC5IB9lqy0/C/ufRhH3ZWCa5aJFwnJ6GzQ/lphEL5Z+rrBG5zj1FTeuiFer VSe6UMtJebhOpVXXU9+f3Nh84BXZj90iSkIe/QQt072iC9sCl4SIpXw5TC3erYi5WUCM EAHQ== X-Gm-Message-State: AKaTC01wOqT48qPnrxPPSTv5P2EnTAkX9UPPelBMKIJXJbrTCU05tgkIhahd+jRRDdTjqtTjqxY= X-Received: by 10.98.84.68 with SMTP id i65mr4906983pfb.133.1479544768902; Sat, 19 Nov 2016 00:39:28 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id v193sm5106241pgb.37.2016.11.19.00.39.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 19 Nov 2016 00:39:27 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Sat, 19 Nov 2016 16:37:19 +0800 Message-Id: <1479544691-59575-5-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> References: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [Patch v4 04/56] Hisilicon/PCIe: support different memory address in PCIe domain X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Most of PCIe memory BARs can only be mapped to 4G above system address, for there is not enough address space under 4G. However, some legacy PCIe devices may require to be mapped into 32bit address. To support such devices, a pair of new parameters is introduced to expose memory address under 4G in PCIe domain, which can be different from the address in system domain, by setting iATU accordingly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 2 ++ .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 6 ++-- Chips/Hisilicon/Include/Library/PlatformPciLib.h | 2 ++ .../D02/Library/PlatformPciLib/PlatformPciLib.c | 32 +++++++++++++++------ .../D03/Library/PlatformPciLib/PlatformPciLib.c | 33 ++++++++++++++++------ 5 files changed, 57 insertions(+), 18 deletions(-) diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index 99c97cf..cddda6b 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -478,6 +478,8 @@ typedef struct { UINT32 SocType; UINT64 CpuMemRegionBase; UINT64 CpuIoRegionBase; + UINT64 PciRegionBase; + UINT64 PciRegionLimit; EFI_DEVICE_PATH_PROTOCOL *DevicePath; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 01aa1e0..03edcf1 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -730,7 +730,7 @@ void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT6 VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private) { - SetAtuMemRW (Private->RbPciBar, Private->MemBase, Private->MemLimit, Private->CpuMemRegionBase, 0); + SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0); SetAtuConfig0RW (Private, 1); SetAtuConfig1RW (Private, 2); SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3); @@ -800,6 +800,8 @@ RootBridgeConstructor ( PrivateData->Ecam = ResAppeture->Ecam; PrivateData->CpuMemRegionBase = ResAppeture->CpuMemRegionBase; PrivateData->CpuIoRegionBase = ResAppeture->CpuIoRegionBase; + PrivateData->PciRegionBase = ResAppeture->PciRegionBase; + PrivateData->PciRegionLimit = ResAppeture->PciRegionLimit; // // Bus Appeture for this Root Bridge (Possible Range) @@ -1058,7 +1060,7 @@ RootBridgeIoMemRW ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); /* Address is bus resource */ - Address -= PrivateData->MemBase; + Address -= PrivateData->PciRegionBase; Address += PrivateData->CpuMemRegionBase; PCIE_DEBUG("RootBridgeIoMemRW Address:0x%llx\n", Address); diff --git a/Chips/Hisilicon/Include/Library/PlatformPciLib.h b/Chips/Hisilicon/Include/Library/PlatformPciLib.h index e3228db..9d28fec 100644 --- a/Chips/Hisilicon/Include/Library/PlatformPciLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformPciLib.h @@ -200,6 +200,8 @@ typedef struct { UINT64 CpuMemRegionBase; UINT64 CpuIoRegionBase; UINT64 RbPciBar; + UINT64 PciRegionBase; + UINT64 PciRegionLimit; } PCI_ROOT_BRIDGE_RESOURCE_APPETURE; extern PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c index b487b5f..797163a 100644 --- a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c @@ -29,7 +29,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB0RB0_PCI_BASE) //RbPciBar + (PCI_HB0RB0_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 1 */ { @@ -42,7 +44,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1, //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, PCI_HB0RB2_CPUIOREGIONBASE, - (PCI_HB0RB1_PCI_BASE) //RbPciBar + (PCI_HB0RB1_PCI_BASE), //RbPciBar + PCI_HB0RB1_PCIREGION_BASE, + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 }, /* Port 2 */ { @@ -55,7 +59,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1, //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, PCI_HB0RB2_CPUIOREGIONBASE, - (PCI_HB0RB2_PCI_BASE) //RbPciBar + (PCI_HB0RB2_PCI_BASE), //RbPciBar + PCI_HB0RB2_PCIREGION_BASE , + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 }, /* Port 3 */ @@ -69,7 +75,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB0RB3_PCI_BASE) //RbPciBar + (PCI_HB0RB3_PCI_BASE), //RbPciBar + 0, + 0 } }, {// HostBridge 1 @@ -84,7 +92,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB0_PCI_BASE) //RbPciBar + (PCI_HB1RB0_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 1 */ { @@ -97,7 +107,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB1_PCI_BASE) //RbPciBar + (PCI_HB1RB1_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 2 */ { @@ -110,7 +122,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB2_PCI_BASE) //RbPciBar + (PCI_HB1RB2_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 3 */ @@ -124,7 +138,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB3_PCI_BASE) //RbPciBar + (PCI_HB1RB3_PCI_BASE), //RbPciBar + 0, + 0 } } }; diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c index a08b461..c58118f 100644 --- a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -37,7 +37,10 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB0_PCI_BASE) //RbPciBar + (PCI_HB0RB0_PCI_BASE), //RbPciBar + PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase + PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit + }, /* Port 1 */ { @@ -50,7 +53,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB1_PCI_BASE) //RbPciBar + (PCI_HB0RB1_PCI_BASE), //RbPciBar + PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit }, /* Port 2 */ { @@ -63,7 +68,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB2_PCI_BASE) //RbPciBar + (PCI_HB0RB2_PCI_BASE), //RbPciBar + PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit }, /* Port 3 */ @@ -77,7 +84,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB0RB3_PCI_BASE) //RbPciBar + (PCI_HB0RB3_PCI_BASE), //RbPciBar + 0, + 0 } }, {// HostBridge 1 @@ -92,7 +101,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB0_PCI_BASE) //RbPciBar + (PCI_HB1RB0_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 1 */ { @@ -105,7 +116,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB1_PCI_BASE) //RbPciBar + (PCI_HB1RB1_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 2 */ { @@ -118,7 +131,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB2_PCI_BASE) //RbPciBar + (PCI_HB1RB2_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 3 */ @@ -132,7 +147,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB3_PCI_BASE) //RbPciBar + (PCI_HB1RB3_PCI_BASE), //RbPciBar + 0, + 0 } } };