From patchwork Sat Nov 19 08:37:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 83093 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp506222qge; Sat, 19 Nov 2016 01:04:36 -0800 (PST) X-Received: by 10.36.50.78 with SMTP id j75mr1980070ita.58.1479546276412; Sat, 19 Nov 2016 01:04:36 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id n72si8206014iod.83.2016.11.19.01.04.36; Sat, 19 Nov 2016 01:04:36 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id F2D2B60836; Sat, 19 Nov 2016 09:04:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 0687F634FE; Sat, 19 Nov 2016 08:46:50 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 5D2F7634C8; Sat, 19 Nov 2016 08:45:45 +0000 (UTC) Received: from mail-pg0-f50.google.com (mail-pg0-f50.google.com [74.125.83.50]) by lists.linaro.org (Postfix) with ESMTPS id 88D6C60D2F for ; Sat, 19 Nov 2016 08:40:27 +0000 (UTC) Received: by mail-pg0-f50.google.com with SMTP id p66so111358709pga.2 for ; Sat, 19 Nov 2016 00:40:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VX6Ym6cDvzB58WFTSkCgDy1Vf6qyR9ZpG0U3Srqy1DY=; b=FRbtfAg4sg3rkNQM8JjyXLUGboj6x/snr35q1BkG6gVSJ5qroBdGeBRmFd+yPUohpO CRB5ZdXhGeIKChCJTXZul9J2HTxRAiqUmc5H70XmpzsXjDiaGRboTVf9SoNtFAnOiRNY 0ktGQir2JkoXeuhANDemyEqW6HGxvh3drHgV8jO0ZevIvWLXi5qAkYLDzeizqcCDNL0h Cx53+gE2sQDl+cIlCayL2Tc2Ps6OUB4KxzKhi+lDWDaC/S7oST0HcUOseiP3IRWbMX90 z3DFpcg9kWZCxhbGn2pGSv7ausmsatZrQHsT9uuQQCVajCKpJJ9jc1iXPcSnYc6FM99H UvDA== X-Gm-Message-State: AKaTC02xdc+QY3NfyFQYL1IDikdJsqLThuLkDaK5n27ywRbMvB1uGPHQYK3kNZp7Z+s4yiM9dxI= X-Received: by 10.98.27.132 with SMTP id b126mr4833826pfb.171.1479544826875; Sat, 19 Nov 2016 00:40:26 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id v193sm5106241pgb.37.2016.11.19.00.40.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 19 Nov 2016 00:40:26 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Sat, 19 Nov 2016 16:37:49 +0800 Message-Id: <1479544691-59575-35-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> References: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [Patch v4 34/56] D02/D03/D05: Support Spd mirror mode X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Add Spd mirror mode related registers definition, this is used by memoryinit binary code,base this definition it could support spd mirror mode to have diffrent configuration about MR register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 6bf323d..c0d3305 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ UINT16 DimmSize; UINT16 DimmSpeed; UINT32 RankSize; + UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode struct DDR_RANK Rank[MAX_RANK_DIMM]; }DDR_DIMM; @@ -337,6 +338,7 @@ typedef struct _MEMORY{ UINT8 Config0; UINT8 marginTest; UINT8 Config1[5]; + UINT8 ErrorBypass; //register of spd mirror mode UINT32 Config2; }MEMORY; @@ -789,6 +791,8 @@ struct ODT_ACTIVE_STRUCT { #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM #define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte