From patchwork Sat Nov 19 08:37:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 83072 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp501541qge; Sat, 19 Nov 2016 00:47:19 -0800 (PST) X-Received: by 10.55.6.12 with SMTP id 12mr4426731qkg.182.1479545239358; Sat, 19 Nov 2016 00:47:19 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id n61si3561948qtd.168.2016.11.19.00.47.19; Sat, 19 Nov 2016 00:47:19 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id EB33B63511; Sat, 19 Nov 2016 08:47:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id ED69460CEC; Sat, 19 Nov 2016 08:42:43 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id C250B60BDE; Sat, 19 Nov 2016 08:42:40 +0000 (UTC) Received: from mail-pg0-f46.google.com (mail-pg0-f46.google.com [74.125.83.46]) by lists.linaro.org (Postfix) with ESMTPS id 72BA660BDE for ; Sat, 19 Nov 2016 08:39:40 +0000 (UTC) Received: by mail-pg0-f46.google.com with SMTP id p66so111353918pga.2 for ; Sat, 19 Nov 2016 00:39:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KA6lSu3v2sovX+hQnN2UQMAjvW0ZOWH7grIJYAL+YA4=; b=OIzO2d4zLEWV4eltKb34hvzpihuaM1MourVa8UVqN4iB5zLTLCpA9CfZ89jbg6DnsJ y/8ac6B/7vWKXPSfg9qrMsthMolHpt+bI4tSvAUWYioXS99I6QL9LwAK15PdDz/Lxy5k DirTNRS7OMtdYdxsNSSyXlwK+Z87mbL0jJYQ/Hkrd0tgLaFtFREdvHgcI8Bifq2iMrx+ EtlONhCwXZLmMfYOUt0+hmYSjdPwV+qK34lpov/eIDzeUTpypSoRx0HeQUy3QzaN4yZ7 3PWQj1eHjd89KKiiNCJ0R0hTz0guGEA8FeACpALmeqTeGJPBCUmZpWq9NiUbNlaxTYu5 XnFA== X-Gm-Message-State: AKaTC00cU+rb0f2OB8FhB7k/UyEkLcABJVDXSMdDVhvH9ynakuVm9Axd3HDLpwzdvk642T/8ux8= X-Received: by 10.99.122.92 with SMTP id j28mr8511086pgn.64.1479544779806; Sat, 19 Nov 2016 00:39:39 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id v193sm5106241pgb.37.2016.11.19.00.39.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 19 Nov 2016 00:39:39 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Sat, 19 Nov 2016 16:37:25 +0800 Message-Id: <1479544691-59575-11-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> References: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [Patch v4 10/56] Hisilicon: Reorder DDR timing parameters by alphabetical X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Order of timing parameters of structure DDR_CHANNEL are changed to be alphabetical, to make it easier to find certain parameter. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index f424ae9..4a690af 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -186,20 +186,20 @@ typedef struct _DDR_Channel{ UINT32 MemSize; UINT32 CLSupport; UINT32 minTck; + UINT32 nAA; UINT32 nCL; - UINT32 nWR; + UINT32 nCCDL; + UINT32 nFAW; UINT32 nRCD; UINT32 nRRD; UINT32 nRRDL; UINT32 nRAS; UINT32 nRC; UINT32 nRFC; - UINT32 nWTR; UINT32 nRTP; - UINT32 nAA; - UINT32 nFAW; UINT32 nRP; - UINT32 nCCDL; + UINT32 nWR; + UINT32 nWTR; UINT8 cwl; //tWL? UINT8 pl; //parity latency UINT8 wr_pre_2t_en;