From patchwork Mon Nov 14 11:29:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 82082 Delivered-To: patch@linaro.org Received: by 10.182.1.168 with SMTP id 8csp1082672obn; Mon, 14 Nov 2016 03:45:01 -0800 (PST) X-Received: by 10.55.81.8 with SMTP id f8mr15866877qkb.101.1479123901881; Mon, 14 Nov 2016 03:45:01 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id x206si14957630qkb.136.2016.11.14.03.45.01; Mon, 14 Nov 2016 03:45:01 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 80785608C8; Mon, 14 Nov 2016 11:45:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id DA53960DD7; Mon, 14 Nov 2016 11:38:14 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id DB76E60D87; Mon, 14 Nov 2016 11:37:46 +0000 (UTC) Received: from mail-pf0-f182.google.com (mail-pf0-f182.google.com [209.85.192.182]) by lists.linaro.org (Postfix) with ESMTPS id 658CD60D87 for ; Mon, 14 Nov 2016 11:33:39 +0000 (UTC) Received: by mail-pf0-f182.google.com with SMTP id 189so29461930pfz.3 for ; Mon, 14 Nov 2016 03:33:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dsRZFQ3WpBtGU/sq2M5l5vLl3f8nDSLLo/QFDa6i5RU=; b=MXl046n07Gyl8BKw5zyI0v8znSg0huTKu+fy0uOTmYepjXDcoKs9w5fztcAj/aWGXf U7ewcHiLNjHnqfXw9KALC1cEo4qlNXhT/SZXfJbQyjrhvMulBkOKJd68zdBJ2k/AA8tV kN7+QU01GwW5oCAIY1YvjeA5J6YgHaFKmXI6b1Y3LpVt6GmFCyjfKlVuNCcrcZX6KFi5 /WMGOnpWH/d8jQoMzxiH7eSA2roY22lAMI4yYgLnenxLLl0WR/8tJ0Tq0DeuXJ94uPdB GbYA+nylwbzXdQNmGqovSy9K1KkLoEEG1X/oSA2vKI/n0X7wt1iM6SgZamsCXm2cBn8A fDBA== X-Gm-Message-State: ABUngveK9SGpI8xb/IQ4lm8RKSwGcCdYwSZX/Sqmr+dXxmV832ZTaIf1HLvIUtsu9vQpcek3h9w= X-Received: by 10.98.150.206 with SMTP id s75mr35536194pfk.155.1479123218758; Mon, 14 Nov 2016 03:33:38 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g82sm34663209pfb.43.2016.11.14.03.33.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Nov 2016 03:33:38 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Mon, 14 Nov 2016 19:29:48 +0800 Message-Id: <1479122995-50330-22-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479122995-50330-1-git-send-email-heyi.guo@linaro.org> References: <1479122995-50330-1-git-send-email-heyi.guo@linaro.org> Cc: Heyi Guo Subject: [Linaro-uefi] [PATCH 21/28] D03: Set PcdArmArchTimerFreqInHz to 0 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" D03 have 66M and 50M two types boards, they refer the different reference clock, set the PCD to 0 so that the code will read frequency from register and be adapted to 66M and 50M boards. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Platforms/Hisilicon/D03/D03.dsc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index b144c57..7167f4d 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -219,7 +219,9 @@ # # ARM Architectual Timer Frequency # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|66000000 + # Set it to 0 so that the code will read frequence from register and be + # adapted to 66M and 50M boards + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0 gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE