From patchwork Thu Nov 10 13:52:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 81654 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp738903qge; Thu, 10 Nov 2016 06:02:16 -0800 (PST) X-Received: by 10.55.52.7 with SMTP id b7mr5571115qka.223.1478786536827; Thu, 10 Nov 2016 06:02:16 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id s185si3394397qkc.314.2016.11.10.06.02.16; Thu, 10 Nov 2016 06:02:16 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 705F960ECD; Thu, 10 Nov 2016 14:02:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id E1B9E60E86; Thu, 10 Nov 2016 13:56:27 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id AAA3460E87; Thu, 10 Nov 2016 13:56:19 +0000 (UTC) Received: from mail-pf0-f176.google.com (mail-pf0-f176.google.com [209.85.192.176]) by lists.linaro.org (Postfix) with ESMTPS id A4ED460854 for ; Thu, 10 Nov 2016 13:53:31 +0000 (UTC) Received: by mail-pf0-f176.google.com with SMTP id 189so147439740pfz.3 for ; Thu, 10 Nov 2016 05:53:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iEKW6jbjgljQYWfGmcZkjI0gN6ph/IidLkotfCdGdFY=; b=HpsnU2lmncdOvFdJwEvhQrGBjrxeLZgWSzheLvPZX/qlu1ghCDrGMB9F56tCZyylwu SrNrt1mcNBYSd6fy77/KAPK9C5pPJ28/oCZMlBRr97ixyE26FgPud3mcMohnxbzf5hgb IHglGKGmgkqgPss9ZZnKeojxSZmf0Z5EgdfqgzCP8waUi7icBBqojdBKS7JxadIdqysG pYNEfbapbH3nniwacpNnBNnmgLqOJQ+x7dHGAcSMMdOZEoDPC+KzQJGZhSb/j1rCJ2SH DvaX2QC1HCKZFucWW0T9GpFXjcwMvncLoyuCoElE0zCz8aJ/ux2KhHyTybtnoe6AdXmC N8kw== X-Gm-Message-State: ABUngveHvHDR5tieUKey1FEkSk2SL5IGDzZN9/PQvfQRTnVNu9X7lE5yq/OH39JOrEWY8gr5kwM= X-Received: by 10.98.160.140 with SMTP id p12mr10227966pfl.122.1478786010801; Thu, 10 Nov 2016 05:53:30 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g78sm7625705pfe.19.2016.11.10.05.53.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Nov 2016 05:53:30 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 10 Nov 2016 21:52:08 +0800 Message-Id: <1478785950-24197-5-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> References: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH 04/27] Hisilicon/PCIe: support multiple MSI target addresses X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" There might be multiple PCIe associated ITS in the system, so we change PCD of MSI target address to a feature PCD and specify the addresses in the code. If ITS is not supported by OS, MSI target address will be set to GIC distributor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 ++- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 12 +++++++++--- Chips/Hisilicon/HisiPkg.dec | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- 4 files changed, 13 insertions(+), 6 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 8659e29..8b10dbc 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -51,9 +51,10 @@ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P gHisiTokenSpaceGuid.Pcdsoctype - gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress + gArmTokenSpaceGuid.PcdGicDistributorBase [FeaturePcd] + gHisiTokenSpaceGuid.PcdIsItsSupported gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable [depex] diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index e58d87c..445b997 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -906,9 +906,15 @@ VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { UINT32 Value = 0; - - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdPcieMsiTargetAddress)); - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c4, 0); + if (FeaturePcdGet (PcdIsItsSupported)) { + //PCIE_SYS_CTRL24_REG is MSI Low address register + //PCIE_SYS_CTRL28_REG is MSI High addres register + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PCIE_ITS_1610[HostBridgeNum][Port]); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, PCIE_ITS_1610[HostBridgeNum][Port] >> 32); + } else { + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PcdGet64 (PcdGicDistributorBase) + 0x40); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, (PcdGet64 (PcdGicDistributorBase) + 0x40) >> 32); + } RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); Value |= (1 << 12); RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index fca0b70..39dd75a 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -267,11 +267,11 @@ gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061 - gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0x0|UINT64|0x00000064 gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056 [PcdsFeatureFlag] gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066 + gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065 diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 942b2b8..7c72c84 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -112,6 +112,7 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE + gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" @@ -309,7 +310,6 @@ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000 - gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0xc6010040 ################################################################################ #