From patchwork Thu Nov 10 13:52:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 81660 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp740588qge; Thu, 10 Nov 2016 06:04:50 -0800 (PST) X-Received: by 10.55.105.129 with SMTP id e123mr6136956qkc.173.1478786690365; Thu, 10 Nov 2016 06:04:50 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id h194si3415056qke.263.2016.11.10.06.04.50; Thu, 10 Nov 2016 06:04:50 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 0085960856; Thu, 10 Nov 2016 14:04:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 78A3760E49; Thu, 10 Nov 2016 13:57:45 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 7D77960E96; Thu, 10 Nov 2016 13:57:41 +0000 (UTC) Received: from mail-pf0-f178.google.com (mail-pf0-f178.google.com [209.85.192.178]) by lists.linaro.org (Postfix) with ESMTPS id B32F360E49 for ; Thu, 10 Nov 2016 13:53:42 +0000 (UTC) Received: by mail-pf0-f178.google.com with SMTP id d2so147364267pfd.0 for ; Thu, 10 Nov 2016 05:53:42 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uD5dxZ2h3stA400e4ShNpIQvmrGnvwP6Lbhn6Zm1tEQ=; b=GCFfBkQpw8dviqAdJtg7oy8p7BkmxHkFBvgGnv0h6QFMBosglKwbevSD+38y9V8yRo gqpzvTYSj8ZlIccFepfc4tPrhQO/pt1APa9/9JQyxIwRyuk7IKdAq8KCX7jeR7ONaars NRMG4WQGezPxtfNh2TAwLCa+Qr8BNXHAcSguqu7rrF+0yFi9EMhf9Yo+jSPPI2cElA3s sEaMnzywtU3MEyPw4litW+C0ryrZIsGwQsOrHd7Ts/LJliTQz+ygXAo11TuQWHQv6eWT mAhnUZv2jd2lcxLLtPcBYh0xlPVHEuY2HjTMvZBKxkPvpmfvc5BcZTGungmB5YAQezFL oC/A== X-Gm-Message-State: ABUngvd2Q+XQj4U6Yk93Gcq212W/v4o55QOy79z78toOY5fprS+HcmcLCcwFAPXiYG+w2fAXIzo= X-Received: by 10.99.237.69 with SMTP id m5mr23845785pgk.94.1478786021899; Thu, 10 Nov 2016 05:53:41 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g78sm7625705pfe.19.2016.11.10.05.53.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Nov 2016 05:53:41 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 10 Nov 2016 21:52:14 +0800 Message-Id: <1478785950-24197-11-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> References: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH 10/27] Hisilicon: Reorder DDR timing parameters by alphabetical X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Order of timing parameters of structure DDR_CHANNEL are changed to be alphabetical, to make it easier to find certain parameter. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 8968b21..e6c0fd4 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -186,20 +186,20 @@ typedef struct _DDR_Channel{ UINT32 MemSize; UINT32 CLSupport; UINT32 minTck; + UINT32 nAA; UINT32 nCL; - UINT32 nWR; + UINT32 nCCDL; + UINT32 nFAW; UINT32 nRCD; UINT32 nRRD; UINT32 nRRDL; UINT32 nRAS; UINT32 nRC; UINT32 nRFC; - UINT32 nWTR; UINT32 nRTP; - UINT32 nAA; - UINT32 nFAW; UINT32 nRP; - UINT32 nCCDL; + UINT32 nWR; + UINT32 nWTR; UINT8 cwl; //tWL? UINT8 pl; //parity latency UINT8 wr_pre_2t_en;