From patchwork Thu Oct 27 03:15:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 79591 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp407500qge; Wed, 26 Oct 2016 20:27:56 -0700 (PDT) X-Received: by 10.237.34.51 with SMTP id n48mr4490917qtc.89.1477538876264; Wed, 26 Oct 2016 20:27:56 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id m190si3061870qkd.35.2016.10.26.20.27.56; Wed, 26 Oct 2016 20:27:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E23C460A38; Thu, 27 Oct 2016 03:27:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 05A0061DA5; Thu, 27 Oct 2016 03:20:41 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3C2C161CD0; Thu, 27 Oct 2016 03:20:36 +0000 (UTC) Received: from mail-pf0-f181.google.com (mail-pf0-f181.google.com [209.85.192.181]) by lists.linaro.org (Postfix) with ESMTPS id A804160D78 for ; Thu, 27 Oct 2016 03:16:48 +0000 (UTC) Received: by mail-pf0-f181.google.com with SMTP id s8so8164668pfj.2 for ; Wed, 26 Oct 2016 20:16:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9jT1A3NT7E2Vb3bdj1iIiFXmfu2xfSaUN2Dj0dQn7uw=; b=KXPS8EjUDtXO2TXvRSHfE7/GuInP9POGRvzzYs1dIuaLcAFoIHm7JGClXTfxFLjHJX 4ZHPuxtzP7NBl5+95KuIGocP6WUXHshFwjgNq/dFFg3QddXazk9VF9mjtR48yldf8PfW uRDs1/u2X8HO3joyZNQWgvm092OAK2w7ZS2tKURB95L5h8xB+FEMbL1FAm+dDo8DgOZS NQ3giqI5I4uvAibZYACXV2HunASzv32hZHTm/p/ip/kbLV0Mi2NpJ5DW7meyD6ZTT7li Ref9Rc90Vb/yB0J0+wVLsU86GisOdEYTBWLndqEjVjAbBcvqn3Y+n+w/scyOX4mtYb+w j2pQ== X-Gm-Message-State: ABUngvcUDyMAOmFmNKdDusPBRHwAU6VnTxM2cLZHKqPGcgwhtyHsxbRLcGfPquhLqgBIDKf73EU= X-Received: by 10.98.142.26 with SMTP id k26mr10123069pfe.26.1477538207981; Wed, 26 Oct 2016 20:16:47 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id h5sm7091734pfg.86.2016.10.26.20.16.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Oct 2016 20:16:47 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 27 Oct 2016 11:15:22 +0800 Message-Id: <1477538129-118465-18-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477538129-118465-1-git-send-email-heyi.guo@linaro.org> References: <1477538129-118465-1-git-send-email-heyi.guo@linaro.org> Cc: Heyi Guo Subject: [Linaro-uefi] [PATCH 19/26] D03: Set PcdArmArchTimerFreqInHz to 0 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Set the PCD to 0 so that the code will read frequency from register and be adapted to 66M and 50M boards. Change-Id: I5ca7e766a592de27c8151752e749e480af896671 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Platforms/Hisilicon/D03/D03.dsc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index b144c57..7167f4d 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -219,7 +219,9 @@ # # ARM Architectual Timer Frequency # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|66000000 + # Set it to 0 so that the code will read frequence from register and be + # adapted to 66M and 50M boards + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0 gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE