From patchwork Thu Oct 27 03:15:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 79589 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp407390qge; Wed, 26 Oct 2016 20:27:29 -0700 (PDT) X-Received: by 10.55.133.198 with SMTP id h189mr5007013qkd.104.1477538849092; Wed, 26 Oct 2016 20:27:29 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id w46si3027533qta.144.2016.10.26.20.27.28; Wed, 26 Oct 2016 20:27:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id B83E560974; Thu, 27 Oct 2016 03:27:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id A7D0061CD0; Thu, 27 Oct 2016 03:20:37 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id BBE2161DA4; Thu, 27 Oct 2016 03:20:33 +0000 (UTC) Received: from mail-pf0-f179.google.com (mail-pf0-f179.google.com [209.85.192.179]) by lists.linaro.org (Postfix) with ESMTPS id 0423161CC5 for ; Thu, 27 Oct 2016 03:16:45 +0000 (UTC) Received: by mail-pf0-f179.google.com with SMTP id e6so8145602pfk.3 for ; Wed, 26 Oct 2016 20:16:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eF/fl9LSckSBwzdLa+JBPpVgocyni6+80mFJrHYg4pA=; b=ZfITog8a0S8p5+TBc6Xuj1WZbmlMNWfIdJTkfs+cJQ69Us8WtUtyVfj+nkTIhg4ELL S+/wCAPrw5y8X3l2y+MjMO0vmaQmD/NYYuk1zqK5UcGqdjdpyexgioW5Hxg0PQUse2oN 1zhul3Ww47lvcNNIs+FeZAkYA/PL5CMD7HSAndQem3Hs3yvfrcdrhzGlK876IBguSoce kqe0KMomwUxcXT9N75h5awY/ScGvhIK7KoQMOlL+RipFCV/xxT8V7zp/P+xVMfSv4MOz NO0garMh5a81s0AtFyAIgB/rmxMjOVARCdn179QPSBZQe2+Sq9ei+cGaTPt4xXpStHiw zkHg== X-Gm-Message-State: ABUngvcfMM1QJoZnCN/5E2dy2MNRhmbVCBhUaBv0nOpIcNyokYC84kgdlZ6Y7C3aOoK4VTczd/w= X-Received: by 10.98.205.207 with SMTP id o198mr10075120pfg.114.1477538204328; Wed, 26 Oct 2016 20:16:44 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id h5sm7091734pfg.86.2016.10.26.20.16.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Oct 2016 20:16:43 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 27 Oct 2016 11:15:20 +0800 Message-Id: <1477538129-118465-16-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477538129-118465-1-git-send-email-heyi.guo@linaro.org> References: <1477538129-118465-1-git-send-email-heyi.guo@linaro.org> Cc: Heyi Guo Subject: [Linaro-uefi] [PATCH 17/26] Hisilicon/SMBIOS: Update ProcessorID from MIDR X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- .../Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 07dae5f..61473e8 100644 --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -226,7 +226,7 @@ GetCacheSocketStr ( OUT CHAR16 *CacheSocketStr ) { - UINTN CacheSocketStrLen = 0; + UINTN CacheSocketStrLen; if(CacheLevel == CPU_CACHE_L1_Instruction) { @@ -258,7 +258,6 @@ UpdateSmbiosCacheTable ( CACHE_SRAM_TYPE_DATA CacheSramType = {0}; CoreCount = 16; // Default value is 16 Core - CacheSize = 0; // // Set Cache Configuration @@ -490,6 +489,7 @@ AddSmbiosProcessorTypeTable ( CHAR16 *CpuVersion; STRING_REF TokenToUpdate; + UINT64 *ProcessorId; Type4Record = NULL; ProcessorManuStr = NULL; ProcessorVersionStr = NULL; @@ -614,6 +614,8 @@ AddSmbiosProcessorTypeTable ( Type4Record->ProcessorCharacteristics = ProcessorCharacteristics.Data; Type4Record->ExternalClock = (UINT16)(ArmReadCntFrq() / 1000 / 1000); + ProcessorId = (UINT64 *)&(Type4Record->ProcessorId); + *ProcessorId = ArmReadMidr(); OptionalStrStart = (CHAR8 *) (Type4Record + 1); UnicodeStrToAsciiStr (ProcessorSocketStr, OptionalStrStart);