From patchwork Tue Oct 18 13:09:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 78016 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp879525qge; Tue, 18 Oct 2016 06:14:40 -0700 (PDT) X-Received: by 10.55.128.3 with SMTP id b3mr516903qkd.52.1476796480378; Tue, 18 Oct 2016 06:14:40 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id y2si20969484qtb.15.2016.10.18.06.14.37; Tue, 18 Oct 2016 06:14:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 79516615E2; Tue, 18 Oct 2016 13:14:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id EECD060E0D; Tue, 18 Oct 2016 13:12:25 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 1F60360C86; Tue, 18 Oct 2016 13:12:06 +0000 (UTC) Received: from mail-pf0-f176.google.com (mail-pf0-f176.google.com [209.85.192.176]) by lists.linaro.org (Postfix) with ESMTPS id 2255960D1A for ; Tue, 18 Oct 2016 13:11:39 +0000 (UTC) Received: by mail-pf0-f176.google.com with SMTP id e6so94374434pfk.3 for ; Tue, 18 Oct 2016 06:11:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D5mI5ww1T1jasXAyByTPAHysIxuTC1TjDA3P49hKpO8=; b=fqvoXd+AjmUAJDfoKM//3NlWzBipg5S+wh6Ng5EJ/TCfgJIXb7d29lWUNJsQObxbL/ 861GmIfxazBoWi9chcGY4IVXfAF0PkCNrAJvG9uLt8+1O1HKrCYhuO4rSXJzbJ8IUQGp s3LwOwT+uWN0SfX6o5kRS7HaqNItCOcnUPb4jumloERpzKUGIWJ7KxI/OewrUsXHliaM ZNQTN4EP4HLBcphAQ+F+ODIMlk4aR8lm6mfYWeNgEBIS2CHO5MclmRLfsg3UJk/4KlbR Yd/aW4BMKIJJbPN3Q8BkcppePZozMdFw0DjB/dhuZmEB7BPQaxc66KS1+MOT9VbyGJQB FTxg== X-Gm-Message-State: AA6/9Rk8LDvrXOVLOo4vZWdXIKRx+S8ca8IUCRo6oSRQnzo8ZKrIwOYyJH8Bo0qpq4j5EMWmXC8= X-Received: by 10.99.49.84 with SMTP id x81mr513769pgx.68.1476796298493; Tue, 18 Oct 2016 06:11:38 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a88sm56088460pfe.21.2016.10.18.06.11.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Oct 2016 06:11:38 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 18 Oct 2016 21:09:52 +0800 Message-Id: <1476796207-94336-9-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> References: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH v2 08/24] Hisilicon/PciHostBridgeDxe: add support for Hi1616 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" PCIe root port controllers on Hi1616 are almost the same with those on Hi1610, but there are some system integration differences. So we set SOC type to a new value but in this driver they will enter the same branch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 03edcf1..91775a9 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -741,7 +741,7 @@ BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port) { UINT32 Value = 0; - if (0x1610 == SocType) + if ((0x1610 == SocType) || (0x1616 == SocType)) { Value = MmioRead32(RbPciBar + 0x131C); if ((Value & 0x3F) == 0x11)