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[54.225.227.206]) by mx.google.com with ESMTP id d5si20915455qkb.276.2016.10.18.06.12.44; Tue, 18 Oct 2016 06:12:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id CC96A60E09; Tue, 18 Oct 2016 13:12:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 3B03F60BDA; Tue, 18 Oct 2016 13:12:10 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 741E360B2A; Tue, 18 Oct 2016 13:12:01 +0000 (UTC) Received: from mail-pf0-f169.google.com (mail-pf0-f169.google.com [209.85.192.169]) by lists.linaro.org (Postfix) with ESMTPS id 7759360B2A for ; Tue, 18 Oct 2016 13:11:26 +0000 (UTC) Received: by mail-pf0-f169.google.com with SMTP id 128so95112312pfz.0 for ; Tue, 18 Oct 2016 06:11:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T5aPCjUM8dDPv1JkHHoTk2p3E1kR4O0cESiYsXkcs04=; b=MNsKN/+U6IHGO4frWR2FfAdjNsDW6Sf6MvjJTKudnnse/pOWwe9++CwISL2q2OKawR hL1YxUSsXFf4Cze7RJaKcOd1dMRDQ8rZfcwFULJ90/jj/zsTVoxiVnWfox6FdhZf7Iwg OLdel1+vPxkWK6Nh1MzPy8ADfoWvXI7tppCPI8ZIUHkiQv6NaGicxo8vrk4zXlj8cAUI iwyh8NCxuSeMnQAbLzPBUKEc3eIGYnXfsseXD69bqOIRLpvEs8LkZELDN7M3yRO40u3h pneGXxM9w1dve7YT7V2J3IkEJ9WMzg7L+f5k0Et9rF2wF+tiyYhrplt+AcJ1YFTYu5Kw EmEw== X-Gm-Message-State: AA6/9Rkd9VLWC40pi0/+9++3PobW/YE/5OrRxLj6MrbGKcu/H+iBY1LqL2nhDIk4tUqvv3yIYUg= X-Received: by 10.98.69.151 with SMTP id n23mr663459pfi.60.1476796285680; Tue, 18 Oct 2016 06:11:25 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a88sm56088460pfe.21.2016.10.18.06.11.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Oct 2016 06:11:25 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 18 Oct 2016 21:09:46 +0800 Message-Id: <1476796207-94336-3-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> References: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH v2 02/24] Hisilicon/PcieInit: fix typo for PCIE_APB_SLAVE_BASE_1610 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" PCIE_APB_SLAVE_BASE_1610 was spelt as PCIE_APB_SLVAE_BASE_1610, and this patch is to fix this typo. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 44 +++++++++++----------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 4ddb116..5c14907 100755 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -27,7 +27,7 @@ UINT64 pcie_subctrl_base_1610[2] = {0xa0000000, 0xb0000000}; UINT64 io_sub0_base = 0xa0000000; UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000}; #define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000)) -UINT64 PCIE_APB_SLVAE_BASE_1610[2][4] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000}, +UINT64 PCIE_APB_SLAVE_BASE_1610[2][4] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000}, {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}}; UINT64 PCIE_PHY_BASE_1610[2][4] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000}, {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}}; @@ -163,9 +163,9 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) if (0x1610 == soctype) { - RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); Value |= BIT11|BIT30|BIT31; - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1); return EFI_SUCCESS; } @@ -197,9 +197,9 @@ EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) if (0x1610 == soctype) { - RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); Value &= ~(BIT11); - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1); return EFI_SUCCESS; } @@ -401,7 +401,7 @@ EFI_STATUS PcieModeSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_P if (0x1610 == soctype) { - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0xf8, 0x4 << 28); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0xf8, 0x4 << 28); } else { @@ -516,10 +516,10 @@ VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) PcieRegWrite(Port, 0x168, 0x44444444); PcieRegWrite(Port, 0x16c, 0x44444444); PcieRegWrite(Port, 0x170, 0x44444444); - RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value); + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value); Value &= (~0x3f); Value |= 0x5; - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value); } else @@ -764,10 +764,10 @@ VOID PciePortNumSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Num if (0x1610 == soctype) { UINT32 Value = 0; - RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value); + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value); Value &= ~(0xff); Value |= Num; - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value); } return; } @@ -777,9 +777,9 @@ VOID PcieLaneReversalSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) UINT32 Value = 0; if (0x1610 == soctype) { - RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value); + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value); Value |= BIT16; - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value); } return; } @@ -809,7 +809,7 @@ BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) U_SC_PCIE0_SYS_STATE4 PcieStat; if (0x1610 == soctype) { - RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x131c, PcieStat.UInt32); + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x131c, PcieStat.UInt32); Value = PcieStat.UInt32; if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE) return TRUE; @@ -842,10 +842,10 @@ VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd) UINT32 Value = 0; if (0x1610 == soctype) { - RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value); + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value); Value &= ~(0xf); Value |= Spd; - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value); return; } return; @@ -855,10 +855,10 @@ VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 { UINT32 Value = 0; { - RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value); + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value); Value &= 0x0000ffff; Value |= 0x06040000; - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value); return; } } @@ -867,11 +867,11 @@ void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { UINT32 Value = 0; - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdPcieMsiTargetAddress)); - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c4, 0); - RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdPcieMsiTargetAddress)); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c4, 0); + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); Value |= (1 << 12); - RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); return; } @@ -894,7 +894,7 @@ PciePortInit ( if (0x1610 == soctype) { - mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][PortIndex]; + mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][PortIndex]; DEBUG((EFI_D_INFO, "Soc type is 1610\n")); } else