From patchwork Tue Oct 18 13:09:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 78027 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp882113qge; Tue, 18 Oct 2016 06:20:01 -0700 (PDT) X-Received: by 10.55.64.21 with SMTP id n21mr384761qka.137.1476796801526; Tue, 18 Oct 2016 06:20:01 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id d28si20967157qte.67.2016.10.18.06.20.01; Tue, 18 Oct 2016 06:20:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2356460BE7; Tue, 18 Oct 2016 13:20:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id D34C2615B0; Tue, 18 Oct 2016 13:13:18 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 4AF8B60DA0; Tue, 18 Oct 2016 13:12:38 +0000 (UTC) Received: from mail-pf0-f179.google.com (mail-pf0-f179.google.com [209.85.192.179]) by lists.linaro.org (Postfix) with ESMTPS id C022260DA0 for ; Tue, 18 Oct 2016 13:11:51 +0000 (UTC) Received: by mail-pf0-f179.google.com with SMTP id 128so95117006pfz.0 for ; Tue, 18 Oct 2016 06:11:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FaMQ5XiojL4d02zP7RSUVvoMdgQKojiGDn+ElOnAhUs=; b=BqVn9mA7pIXeMiNqKa2xwXQ1fYp6c33qfmTNjC7VjDlWbR7G6ZiZeiGI3/DRqyTTxr 60P3wgjoA+2+mANjGzOCNsi0Gc/IiuwcDXy/6u9Zsu+b1FUmR2tgLY5luGtIROk7P8Rn SL4HydoYaQVrUyzND/bZRMjht9oWAfiLONVBdDZkVcBJ/ZE3h+D9RZ1um4dXq7Khh5fU IQieSM0xZc7LQq2VSc4CAx9rDtx3gEF4qXxVhx/4Te/i92sP99OxijTyJIplZ5lOgJp1 1ZOxkVMNdrP3LiQQEAFZpQah2dQVepbxNp1XSUwjujGJShDrjGGGKim0kMAVhTSIuyrf zHsQ== X-Gm-Message-State: AA6/9Rn/M3DCyd1m5siNKpMXPkR5gt4h4NvdP7rFrBW9DkZtVEFzcVpvMmJ1g9hb76SOmt86ouI= X-Received: by 10.98.60.17 with SMTP id j17mr676756pfa.52.1476796311153; Tue, 18 Oct 2016 06:11:51 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a88sm56088460pfe.21.2016.10.18.06.11.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Oct 2016 06:11:48 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 18 Oct 2016 21:09:58 +0800 Message-Id: <1476796207-94336-15-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> References: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH v2 14/24] Hisilicon/HwMemInitLib.h: fix typo for phyDqsFallRiseDelay X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" phyDqsFallRiseDelay was spelt as phyDqs*Fail*RiseDelay; just fix the typo. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index f424ae9..8968b21 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -228,7 +228,7 @@ typedef struct _DDR_Channel{ UINT8 per_cs_training_en; UINT32 phyRdDataEnIeDly; UINT32 phyPadCalConfig; - UINT32 phyDqsFailRiseDelay; + UINT32 phyDqsFallRiseDelay; UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency;