From patchwork Tue Oct 18 13:09:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 78019 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp879855qge; Tue, 18 Oct 2016 06:15:16 -0700 (PDT) X-Received: by 10.55.103.69 with SMTP id b66mr428915qkc.108.1476796516052; Tue, 18 Oct 2016 06:15:16 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id r202si20602888qke.6.2016.10.18.06.15.15; Tue, 18 Oct 2016 06:15:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id A36FF60DEF; Tue, 18 Oct 2016 13:15:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 39C8060D7E; Tue, 18 Oct 2016 13:12:37 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 0C89B60C86; Tue, 18 Oct 2016 13:12:08 +0000 (UTC) Received: from mail-pf0-f169.google.com (mail-pf0-f169.google.com [209.85.192.169]) by lists.linaro.org (Postfix) with ESMTPS id 3C6B760D49 for ; Tue, 18 Oct 2016 13:11:41 +0000 (UTC) Received: by mail-pf0-f169.google.com with SMTP id r16so71073222pfg.1 for ; Tue, 18 Oct 2016 06:11:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=r2GqzixHurPHSGgwQggvtLsHclN4GaYhrWSwFGat32A=; b=IurWDcYghZcsNmXviukZ/zHxhCtPBn52Xl4mAazTUpbr8oFuZgmHbGoatm6f8UlhA5 fgwPKoGCaKavw616pRgC5fGfkuxgtzGF5xBvPbDl1y+W9RDq0/GSK1X2aiS8BT/K70hy Rd+k9maV6ZwZoHOLsakCCrATDuwlYpJ8cau7XAukp/bMVMuAnckxpXGnoRmP16tCdeJ4 EzkhzU/Hv0A4d41FWHq5RT3WFVSHDKDb+jZ8xVMPca/lCzwageLQl23hiWM8CaR7fndk 3ZwgqsLBFV3x1r1R5RV5GyYgGCn9yG8EJ4Iv9JzbkDSUZogbnZgWcREY0M1JehScM9oh 6ETg== X-Gm-Message-State: AA6/9RmyyvDyaL8hGuoStyGcMXLAFT0RJ5f93vlAJx68L7oFp/otDHpwgsrDGG17ZIHPTr+LY9M= X-Received: by 10.98.138.79 with SMTP id y76mr627987pfd.158.1476796300502; Tue, 18 Oct 2016 06:11:40 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a88sm56088460pfe.21.2016.10.18.06.11.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Oct 2016 06:11:39 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 18 Oct 2016 21:09:53 +0800 Message-Id: <1476796207-94336-10-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> References: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH v2 09/24] Hisilicon/PCIeInit: Remove unused function PciePortReset X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The PciePortReset function is unuesed, so we remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 38 ---------------------- 1 file changed, 38 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index fa48a6e..85fd319 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -584,44 +584,6 @@ VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) } -EFI_STATUS PciePortReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - if(Port >= PCIE_MAX_PORT_NUM) - { - return EFI_INVALID_PARAMETER; - } - - - if(PcieIsLinkUp(soctype, HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port]) - { - (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port); - } - - mPcieIntCfg.PortIsInitilized[Port] = FALSE; - mPcieIntCfg.DmaResource[Port] = (VOID *)NULL; - mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0; - mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0; - ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U)); - - if(Port <= 2) - { - RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1); - MicroSecondDelay(0x1000); - - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1); - MicroSecondDelay(0x1000); - } - else - { - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1); - MicroSecondDelay(0x1000); - - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1); - MicroSecondDelay(0x1000); - } - return EFI_SUCCESS; -} - EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { UINT32 PortIndexInSicl;