From patchwork Thu Oct 13 02:00:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 77598 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp14872qge; Wed, 12 Oct 2016 19:01:10 -0700 (PDT) X-Received: by 10.55.192.130 with SMTP id v2mr3789507qkv.162.1476324070394; Wed, 12 Oct 2016 19:01:10 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id m52si5247297qta.84.2016.10.12.19.01.10; Wed, 12 Oct 2016 19:01:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 179176175D; Thu, 13 Oct 2016 02:01:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 14F9361749; Thu, 13 Oct 2016 02:00:48 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id AF7C661749; Thu, 13 Oct 2016 02:00:42 +0000 (UTC) Received: from mail-pf0-f178.google.com (mail-pf0-f178.google.com [209.85.192.178]) by lists.linaro.org (Postfix) with ESMTPS id 40EC360D8A for ; Thu, 13 Oct 2016 02:00:40 +0000 (UTC) Received: by mail-pf0-f178.google.com with SMTP id r16so3528962pfg.1 for ; Wed, 12 Oct 2016 19:00:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vqUN8KJr0dDyke/ULkeqMKUC2j57s9ubo3fXPvTrYzA=; b=BioqlcHHNJezsZ8Zzbg+Fu/byAnSuCvbXImStrxBcipZggN7CcJiG675JbMCMmikw8 ULGuW5Cc+yWSYbd9jY8ylTuQdmilRT2OacIoU7G4lWZBKc5QvbbCS7Ot5cFeozsyqr2y zFKidXzfQG/agz/lBHWCVgzycwrzFUosQ9xb/Buu/TVwmIHl0d9jjR/rInJoL6M/NHuC 69vQpkEu5jhw/EjbJKq3KPaMjzoyTNnpmXsv2PbiLcgquKrxSQE14WKpM9b+kmFZ+ir6 C18Sf5C+1nemJ45kzVRTAAfoSBu8dR1Ej583rXditnHfBRjOF7KlxrEx7go3+bhKFIKm mgUg== X-Gm-Message-State: AA6/9RmZDDgm2KzkbQALNDMQupHOFc+1OjhFNs5XktWOirKfOHQyNttNHVIWbottPt7YbtpCrOk= X-Received: by 10.98.133.21 with SMTP id u21mr6375887pfd.157.1476324039573; Wed, 12 Oct 2016 19:00:39 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id sv8sm14732756pab.18.2016.10.12.19.00.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 12 Oct 2016 19:00:39 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 13 Oct 2016 10:00:11 +0800 Message-Id: <1476324020-57155-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476324020-57155-1-git-send-email-heyi.guo@linaro.org> References: <1476324020-57155-1-git-send-email-heyi.guo@linaro.org> Cc: hensonwang Subject: [Linaro-uefi] [PATCH 02/11] Hisilicon/Hi1610/PCIe: Added performance tuning X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang Signed-off-by: Heyi Guo --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 65 ++++++++++++++++++++++ Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 1 + 2 files changed, 66 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 4ddb116..d2928ee 100755 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -185,6 +185,70 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) } +EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) +{ + UINT32 Value = 0; + + if(Port >= PCIE_MAX_PORT_NUM) + { + return EFI_INVALID_PARAMETER; + } + + if (0x1610 == soctype) + { + //PCIe_SYS_CTRL13 + RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL13_REG, Value); + Value |= (BIT13 | BIT12); + Value |= BIT10; + RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL13_REG, Value); + + //PCIe_SYS_CTRL6 + RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + PCIE_CTRL_6_REG, Value); + Value |= (BIT13 | BIT12); + Value |= (BIT17 | BIT19 | BIT21 | BIT23 | BIT25 | BIT27 | BIT29); + RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + PCIE_CTRL_6_REG, Value); + + //PCIe_SYS_CTRL54 + RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL54_REG, Value); + Value &= ~(BIT30); + Value &= ~(0xff<<16); + RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL54_REG, Value); + + //PCIe_SYS_CTRL19 + RegRead(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL19_REG, Value); + Value |= (BIT28 | BIT30); + RegWrite(PCIE_APB_SLVAE_BASE_1610[HostBridgeNum][Port] + 0x1000 + PCIE_SYS_CTRL19_REG, Value); + } + else + { + PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); + //PCIe_SYS_CTRL13 + PcieRegRead(Port, PCIE_SYS_CTRL13_REG); + Value |= ((BIT13) | (BIT12)); + Value |= (BIT10); + PcieRegWrite(Port, PCIE_SYS_CTRL13_REG, Value); + + //PCIe_SYS_CTRL6 + PcieRegRead(Port, PCIE_CTRL_6_REG); + Value |= ((BIT13) | (BIT12)); + Value |= ((BIT17) | (BIT19) | (BIT21) | (BIT23) | (BIT25) | (BIT27) | (BIT29)); + PcieRegWrite(Port, PCIE_CTRL_6_REG, Value); + + //PCIe_SYS_CTRL54 + PcieRegRead(Port, PCIE_SYS_CTRL54_REG); + Value &= ~(BIT30); + Value &= ~(0xff<<16); + PcieRegWrite(Port, PCIE_SYS_CTRL54_REG, Value); + + //PCIe_SYS_CTRL19 + PcieRegRead(Port, PCIE_SYS_CTRL19_REG); + Value |= ((BIT28) | (BIT30)); + PcieRegWrite(Port, PCIE_SYS_CTRL19_REG, Value); + PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); + } + return EFI_SUCCESS; +} + EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { PCIE_CTRL_7_U pcie_ctrl7; @@ -940,6 +1004,7 @@ PciePortInit ( /* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); + (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex); PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex); /* diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index bdd80f8..539d567 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -8981,6 +8981,7 @@ typedef union tagIepMsiCtrlIntStatus #define PCIE_SYS_CTRL24_REG (PCI_SYS_BASE + 0x1b4) #define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) #define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) +#define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) #define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) #define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) #define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38)