From patchwork Fri May 13 16:37:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 67793 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp360339qge; Fri, 13 May 2016 09:38:20 -0700 (PDT) X-Received: by 10.140.92.65 with SMTP id a59mr15814755qge.93.1463157500241; Fri, 13 May 2016 09:38:20 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id u76si11736512qke.89.2016.05.13.09.38.19; Fri, 13 May 2016 09:38:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id C49536160E; Fri, 13 May 2016 16:38:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id ADB5E61650; Fri, 13 May 2016 16:37:56 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id ED4F56157E; Fri, 13 May 2016 16:37:51 +0000 (UTC) Received: from mail-wm0-f43.google.com (mail-wm0-f43.google.com [74.125.82.43]) by lists.linaro.org (Postfix) with ESMTPS id 0AA206157E for ; Fri, 13 May 2016 16:37:51 +0000 (UTC) Received: by mail-wm0-f43.google.com with SMTP id g17so39145186wme.1 for ; Fri, 13 May 2016 09:37:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/V7aME5oyJVKHomCXKdJUKgeJgRf8PDij3lQgqLPpaU=; b=J0EtMbyCOYLhp67OHACULrM22AA7L4WQR1ThgX6WSdOrU0p7oUwAB5dHF+on3mRaiD F9+SSry5H3iZex+fsm1CoUYXecLA9ied+fGvCrw3erybyq8x7zvhK2xS8nlp8tFSx9Ei TFYFeZ27Wf6LI7Q+8GDlXyyuU6WwpYu/LLsZgoa5rhdFcYOz+rYoCTcWuny5f6NDGswC HlP6xCFZ+yPMTadH/MsUYD25FFOXQkFOUoI2kdmv7fmLdgV43SG4hfj9b1J8jKqgl969 pxBOsnTqc4rtLkOpjs9BItc2CI8Ls5hWP8iPW1CDQ3oDZtz3rsd1vdPxNSTla8Zwl4K8 8QNg== X-Gm-Message-State: AOPr4FVzav0QpN2E6zGJR3C9KgiWZwLLJCnRZpQrYDztMzqFU54MB5NDM/gXDHD3/BsJbhCHz8Y= X-Received: by 10.28.156.195 with SMTP id f186mr4597733wme.74.1463157470274; Fri, 13 May 2016 09:37:50 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id e16sm4092904wmc.3.2016.05.13.09.37.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 May 2016 09:37:49 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Fri, 13 May 2016 18:37:09 +0200 Message-Id: <1463157431-22988-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1463157431-22988-1-git-send-email-ard.biesheuvel@linaro.org> References: <1463157431-22988-1-git-send-email-ard.biesheuvel@linaro.org> Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH 3/5] Platforms/AMD/StyxSpiFvDxe: use PCD for base of flash address X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Now that STYX_EFI.fd covers the entire SPI flash, we can use its base address in the SPI flash driver to calculate the LBA offset of writes into the in-memory shadow region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c index e27d9afd6c22..7ccfd7f75b19 100644 --- a/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c +++ b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c @@ -25,9 +25,7 @@ #include #include -// TODO: replace with FixedPcdGet64 (PcdFdBaseAddress) once we have updated -// the .FDF to let STYX_EFI.fd cover the entire SPI flash -#define SPI_BASE 0x8000C80000UL +#define SPI_BASE (FixedPcdGet64 (PcdFdBaseAddress)) #define BLOCK_SIZE (FixedPcdGet32 (PcdFlashNvStorageBlockSize)) STATIC AMD_ISCP_DXE_PROTOCOL *mIscpDxeProtocol;