From patchwork Tue May 10 15:01:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 67458 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp2175584qge; Tue, 10 May 2016 08:01:47 -0700 (PDT) X-Received: by 10.55.47.70 with SMTP id v67mr42763413qkh.135.1462892507497; Tue, 10 May 2016 08:01:47 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id 1si1684174qkk.154.2016.05.10.08.01.47; Tue, 10 May 2016 08:01:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E97F76163B; Tue, 10 May 2016 15:01:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 8E93B610DE; Tue, 10 May 2016 15:01:45 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 93B6261585; Tue, 10 May 2016 15:01:44 +0000 (UTC) Received: from mail-wm0-f41.google.com (mail-wm0-f41.google.com [74.125.82.41]) by lists.linaro.org (Postfix) with ESMTPS id C1163610DE for ; Tue, 10 May 2016 15:01:43 +0000 (UTC) Received: by mail-wm0-f41.google.com with SMTP id n129so182717456wmn.1 for ; Tue, 10 May 2016 08:01:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=wfGokUUI6g9acoa5S+Ic5ySJwgDZ3kHZyequVneJJWo=; b=aXj/Jqnfwtl7xPFFgGuq9nEgqCHvUpeqB6Wj1nRIlqqcynY12EcVM5o2iv4MY4bylt I5FAF+ntU8P5p+KcfblZSNJp1bsqnh3FudhxmOvfRISfgQWDlgT4X/spbuV0yz4n6ERC uhDgM2KGHLsFwaYkrDtjT1dXQePYU3wpHFBrBaNMcPoLGCnwPl/nuxjV0LXmByftYbxM TzqxzVN7b0zv4IxNXae6t/rIzrRP174FlaMYWathSL5pOn8kqlsPemus8CHiBhe3kUbe pjjjKA35gzhcOeSdT187IlXo931hYy832CIemjQZ1UNpqWIl7y75qIyas0TpQU9VkVle xAEg== X-Gm-Message-State: AOPr4FV5RAt+XmEtkPJDwQFxuv7hWpURCvWXKpcJ+1UnQD6JUds6gNbRg+uIu8LFrSOzXvdsGlY= X-Received: by 10.194.58.162 with SMTP id s2mr27124651wjq.53.1462892502916; Tue, 10 May 2016 08:01:42 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id q77sm30732927wmd.12.2016.05.10.08.01.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 10 May 2016 08:01:41 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Tue, 10 May 2016 17:01:37 +0200 Message-Id: <1462892497-31132-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH] Platforms/AMD/Styx/AmdStyxPciHostBridgeLib: set unused regions base to MAX_UINT64 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" An upcoming fix to the generic PciHostBridgeDxe driver code requires that the limit of an unused region does not exceed the base, since they describe a 1 byte region if base equals limit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c index 432e4230a59b..8d8c76a0f7f6 100644 --- a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c +++ b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c @@ -106,9 +106,9 @@ PciHostBridgeGetRootBridges ( // // No separate ranges for prefetchable and non-prefetchable BARs // - RootBridge->PMem.Base = 0; + RootBridge->PMem.Base = MAX_UINT64; RootBridge->PMem.Limit = 0; - RootBridge->PMemAbove4G.Base = 0; + RootBridge->PMemAbove4G.Base = MAX_UINT64; RootBridge->PMemAbove4G.Limit = 0; ASSERT (FixedPcdGet64 (PcdPciMmio32Translation) == 0);