From patchwork Mon May 2 13:35:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 67028 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp46888qge; Mon, 2 May 2016 06:36:34 -0700 (PDT) X-Received: by 10.140.238.76 with SMTP id j73mr34069379qhc.24.1462196194843; Mon, 02 May 2016 06:36:34 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id n125si14612189qkb.263.2016.05.02.06.36.34; Mon, 02 May 2016 06:36:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8A80161646; Mon, 2 May 2016 13:36:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 48455615F3; Mon, 2 May 2016 13:36:12 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 1020661601; Mon, 2 May 2016 13:36:08 +0000 (UTC) Received: from mail-wm0-f54.google.com (mail-wm0-f54.google.com [74.125.82.54]) by lists.linaro.org (Postfix) with ESMTPS id 7333461605 for ; Mon, 2 May 2016 13:35:56 +0000 (UTC) Received: by mail-wm0-f54.google.com with SMTP id e201so107322986wme.0 for ; Mon, 02 May 2016 06:35:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fqbkUgujaNXrPUjaTEB5FuPSXZML3Jy9zfk7G8xSogE=; b=IECg+mM61B6fxESuzkmVcjKDKZArx/FooiiVQm64ez4rLH8eVehMPgEmibON8rhFRa W/i+Tz2uU2MRxXesYoOFXnPMRUL42VFOBKNJ/BmDVn2htutC3BBqLykl35DBosNnGhN7 a3FOFJxyNDSaM89ISMptTMLd/koBiINpaC3J23Sd9eqHNXaJDOUdtPsiUF7T9c7BQCms VdZ/uAGevdxx7PMx29UeR4TrxYRFCfz2QpS1Hh5r+Zx9ceaqHOF+MpDqP8JNRFDGdCYh 9NvAChTcI5WwMkCsfWtCXcXkGcInuyybkbM+nXTeYQ8v6obgma9bcM6FHnvdWeUpQI9U Ksfw== X-Gm-Message-State: AOPr4FWaZ2wq4j521D1X0//9BLnFmRKTHFIRN7LmsFjsv/TBIOCb805GfRQJdOCsqo64xgVysVI= X-Received: by 10.194.136.203 with SMTP id qc11mr4927760wjb.42.1462196155579; Mon, 02 May 2016 06:35:55 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id d1sm30424544wjb.47.2016.05.02.06.35.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 May 2016 06:35:54 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Mon, 2 May 2016 15:35:40 +0200 Message-Id: <1462196143-21998-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1462196143-21998-1-git-send-email-ard.biesheuvel@linaro.org> References: <1462196143-21998-1-git-send-email-ard.biesheuvel@linaro.org> Cc: leo.duran@amd.com Subject: [Linaro-uefi] [RFC PATCH 4/7] Platforms/Styx: stop using the ArmMpCoreInfo configuration table X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The ArmMpCoreInfo configuration table describes the secondary cores that are penned up in PrePeiCore/PrePi and waiting for an SGI to proceed with booting into the next pen. Since this approach is unsafe under a PrePeiCore or PrePi that does not execute in place from flash, move to the platform specific gAmdStyxMpCoreInfoGuid HOB that describes the cores, but does not boot them until we are ready to move them straight into the new pen that we will hand to the OS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/AcpiTables/Madt.c | 11 ++++------- Platforms/AMD/Styx/Drivers/FdtDxe/AArch64/BdsLinuxLoader.c | 7 ++----- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/Platforms/AMD/Styx/AcpiTables/Madt.c b/Platforms/AMD/Styx/AcpiTables/Madt.c index c9ee626d7472..ac98693d5f0f 100644 --- a/Platforms/AMD/Styx/AcpiTables/Madt.c +++ b/Platforms/AMD/Styx/AcpiTables/Madt.c @@ -271,18 +271,15 @@ MadtHeader ( EFI_ACPI_5_1_GIC_STRUCTURE *GicC; EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD; EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM; - ARM_PROCESSOR_TABLE *ArmProcessorTable; ARM_CORE_INFO *ArmCoreInfoTable; - UINT32 CoreCount, CpuNum; + UINTN CoreCount, CpuNum; EFI_STATUS Status; - // Get pointer to ARM processor table - ArmProcessorTable = AmdStyxGetArmProcessorTable(); - ASSERT_EFI_ERROR (ArmProcessorTable == NULL); - ArmCoreInfoTable = ArmProcessorTable->ArmCpus; + // Get pointer to ARM core info table + ArmCoreInfoTable = AmdStyxGetArmCoreInfoTable (&CoreCount); + ASSERT (ArmCoreInfoTable != NULL); // Make sure SoC's core count does not exceed what we want to build - CoreCount = ArmProcessorTable->NumberOfEntries; ASSERT (CoreCount <= NUM_CORES); ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount)); diff --git a/Platforms/AMD/Styx/Drivers/FdtDxe/AArch64/BdsLinuxLoader.c b/Platforms/AMD/Styx/Drivers/FdtDxe/AArch64/BdsLinuxLoader.c index 9ec9e1d5061a..0fb2f4e47dd2 100644 --- a/Platforms/AMD/Styx/Drivers/FdtDxe/AArch64/BdsLinuxLoader.c +++ b/Platforms/AMD/Styx/Drivers/FdtDxe/AArch64/BdsLinuxLoader.c @@ -46,7 +46,6 @@ AmdStyxMoveParkedCores( EFI_PHYSICAL_ADDRESS PenBase; UINTN PenSize; UINTN MailboxBase; - ARM_PROCESSOR_TABLE *ArmProcessorTable; ARM_CORE_INFO *ArmCoreInfoTable; UINTN ArmCoreCount; UINTN CoreNum; @@ -54,10 +53,8 @@ AmdStyxMoveParkedCores( UINTN CoreParking; // Get core information - ArmProcessorTable = AmdStyxGetArmProcessorTable(); - ASSERT_EFI_ERROR (ArmProcessorTable == NULL); - ArmCoreInfoTable = ArmProcessorTable->ArmCpus; - ArmCoreCount = ArmProcessorTable->NumberOfEntries; + ArmCoreInfoTable = AmdStyxGetArmCoreInfoTable (&ArmCoreCount); + ASSERT (ArmCoreInfoTable != NULL); // Get Parking area (4KB-aligned, 4KB per core) MpParkingBase = FixedPcdGet64 (PcdParkingProtocolBase);