From patchwork Sat Apr 8 17:14:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 97052 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp744175qgd; Sat, 8 Apr 2017 10:15:15 -0700 (PDT) X-Received: by 10.55.189.130 with SMTP id n124mr45939030qkf.235.1491671715096; Sat, 08 Apr 2017 10:15:15 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id p8si8795803qtp.301.2017.04.08.10.15.14; Sat, 08 Apr 2017 10:15:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 4CD3260943; Sat, 8 Apr 2017 17:15:08 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 383626071A; Sat, 8 Apr 2017 17:15:06 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 14DFC6072E; Sat, 8 Apr 2017 17:15:05 +0000 (UTC) Received: from mail-wm0-f46.google.com (mail-wm0-f46.google.com [74.125.82.46]) by lists.linaro.org (Postfix) with ESMTPS id D280860675 for ; Sat, 8 Apr 2017 17:15:02 +0000 (UTC) Received: by mail-wm0-f46.google.com with SMTP id t189so11544010wmt.1 for ; Sat, 08 Apr 2017 10:15:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=2LILQhewBOZTzCmLzvx7u+3xTT5dBy8OXo9PN23d8A8=; b=Gtt7cW7CVxjstbR2UQ2LX+W1g9H2JCHOtsCRNsqLB/Gp+2Xqs18ehaBINvNK/dqk66 bLvl60vObLbeTvwfiCwUDqffqutMq6K4gXTgKNU7oCi6F7V+yIed8pURSacnt+FqWTLJ N/m0F+ANIYDNtzJlXvIK6kSybj2gK9TweODX4BHT+vaVkEYqEPOtseTzqaLXUf8KNOzN QSDmIMbBowWi3D0NxYbTkdbAK5EHRN8NBr/cS1LdFzIg2eoPKy/rJNYq/YTkXiAQyHbK Co2jTijb+LAKIb8Tz7CjaaolUhe9l4pGNMT6JA/dABdrmADN5ZRIDzvkotUOn5SFRT4X p/iQ== X-Gm-Message-State: AN3rC/7imZXySlPt2UHJfVyQQGNQTfWDGVJbPj23pHxeb3J0ZmeqwaFnIHTfDracujOQALYHQ+M= X-Received: by 10.28.141.12 with SMTP id p12mr3731690wmd.18.1491671701874; Sat, 08 Apr 2017 10:15:01 -0700 (PDT) Received: from localhost.localdomain ([196.81.139.226]) by smtp.gmail.com with ESMTPSA id n13sm3369155wmi.28.2017.04.08.10.14.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Apr 2017 10:15:01 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Sat, 8 Apr 2017 18:14:51 +0100 Message-Id: <20170408171453.13450-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 Cc: alan@softiron.co.uk, lorenzo.pieralisi@arm.com Subject: [Linaro-uefi] [PATCH v2 0/2] Platforms/AMD: fix legacy interrupt routing X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Update the DTS and ACPI descriptions with correct information about the routing of legacy interrupts. For DT, this comes down to updating the interrupt-map with distinct sets of 4 GIC interrupt lines per PCIe slot. For ACPI, we need to update the PNP0A08 node and add three companion devices, one for each slot, whose _PRT methods describe the legacy interrupt routing of each respective slot. The _PRT method at the root of the PCI ACPI hierarchy is updated to map INTA (which is shared by all functions of the bridge device) to GIC interrupt #320. With this change, the boot log is free of warnings and non-MSI capable devices work as expected. Tested on Cello with xhci_hcd.quirks=64 passed on the kernel command line, in which case the xhci interrupt is routed to GIC interrupt #324 Ard Biesheuvel (2): Platforms/AMD: correct legacy PCI interrupt routing in DSDT Platforms/AMD: correct legacy PCI interrupt routing in DTS Platforms/AMD/Styx/AcpiTables/Dsdt.asl | 63 +++++++++++--------- Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 7973 -> 8123 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 20 +++++-- 3 files changed, 49 insertions(+), 34 deletions(-) Reviewed-by: Leif Lindholm