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USB31DRD phy support for Google Tensor gs101 (HS & SS)
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| 7 patches
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[v2,7/7] phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)
USB31DRD phy support for Google Tensor gs101 (HS & SS)
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-
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2024-05-01
André Draszik
New
[v2,6/7] phy: exynos5-usbdrd: convert to clk_bulk for phy (register) access
USB31DRD phy support for Google Tensor gs101 (HS & SS)
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-
-
2024-05-01
André Draszik
New
[v2,5/7] phy: exynos5-usbdrd: uniform order of register bit macros
USB31DRD phy support for Google Tensor gs101 (HS & SS)
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-
-
2024-05-01
André Draszik
New
[v2,4/7] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()
USB31DRD phy support for Google Tensor gs101 (HS & SS)
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-
-
2024-05-01
André Draszik
Superseded
[v2,3/7] phy: exynos5-usbdrd: support isolating HS and SS ports independently
USB31DRD phy support for Google Tensor gs101 (HS & SS)
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-
-
2024-05-01
André Draszik
Superseded
[v2,2/7] phy: exynos5-usbdrd: use exynos_get_pmu_regmap_by_phandle() for PMU regs
USB31DRD phy support for Google Tensor gs101 (HS & SS)
-
-
-
2024-05-01
André Draszik
New
[v2,1/7] dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible
USB31DRD phy support for Google Tensor gs101 (HS & SS)
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-
-
2024-05-01
André Draszik
New
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