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[07/10,V3] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

Message ID 1340971240-18373-8-git-send-email-rajeshwari.s@samsung.com
State Superseded
Headers show

Commit Message

Rajeshwari Shinde June 29, 2012, noon UTC 
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
Changes in V2:
	- None
Changes in V3:
	- Incorported review comments from Minkyu Kang.
 arch/arm/cpu/armv7/exynos/clock.c        |   12 +++++++++++-
 arch/arm/include/asm/arch-exynos/clock.h |    3 +++
 2 files changed, 14 insertions(+), 1 deletions(-)
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..dbd5f11 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@  static unsigned long exynos5_get_pll_clk(int pllreg)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned long r, m, p, s, k = 0, mask, fout;
-	unsigned int freq;
+	unsigned int freq, pll_div2_sel,  mpll_fout_sel;
 
 	switch (pllreg) {
 	case APLL:
@@ -155,6 +155,16 @@  static unsigned long exynos5_get_pll_clk(int pllreg)
 		fout = m * (freq / (p * (1 << (s - 1))));
 	}
 
+	/* According to the user manual, in EVT1 MPLL always gives
+	 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+	if (pllreg == MPLL) {
+		pll_div2_sel = readl(&clk->pll_div2_sel);
+		mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+				& MPLL_FOUT_SEL_MASK;
+		if (mpll_fout_sel == 0)
+			fout /= 2;
+	}
+
 	return fout;
 }
 
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index 90271f1..bf41c19 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -596,4 +596,7 @@  struct exynos5_clock {
 	unsigned char	res123[0xf5d8];
 };
 #endif
+
+#define MPLL_FOUT_SEL_SHIFT	4
+#define MPLL_FOUT_SEL_MASK	0x1
 #endif