| Message ID | 20170302195337.31558-11-alex.bennee@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | MTTCG fixups for 2.9 | expand |
On 03/02/2017 08:53 PM, Alex Bennée wrote: > ..just like the rest of the displayed ESR register. Otherwise people > might scratch their heads if a not obviously hex number is displayed > for the EC field. > > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 3f4211b572..76b608f0ba 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6857,7 +6857,7 @@ void arm_cpu_do_interrupt(CPUState *cs) > new_el); > if (qemu_loglevel_mask(CPU_LOG_INT) > && !excp_is_internal(cs->exception_index)) { > - qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n", > + qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", > env->exception.syndrome >> ARM_EL_EC_SHIFT, > env->exception.syndrome); > } > This seems OK to me. Reviewed-by: KONRAD Frederic <fred.konrad@greensocs.com>
On 2 March 2017 at 19:53, Alex Bennée <alex.bennee@linaro.org> wrote: > ..just like the rest of the displayed ESR register. Otherwise people > might scratch their heads if a not obviously hex number is displayed > for the EC field. > > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 3f4211b572..76b608f0ba 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6857,7 +6857,7 @@ void arm_cpu_do_interrupt(CPUState *cs) > new_el); > if (qemu_loglevel_mask(CPU_LOG_INT) > && !excp_is_internal(cs->exception_index)) { > - qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n", > + qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", > env->exception.syndrome >> ARM_EL_EC_SHIFT, > env->exception.syndrome); > } > -- Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f4211b572..76b608f0ba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6857,7 +6857,7 @@ void arm_cpu_do_interrupt(CPUState *cs) new_el); if (qemu_loglevel_mask(CPU_LOG_INT) && !excp_is_internal(cs->exception_index)) { - qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n", + qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", env->exception.syndrome >> ARM_EL_EC_SHIFT, env->exception.syndrome); }
..just like the rest of the displayed ESR register. Otherwise people might scratch their heads if a not obviously hex number is displayed for the EC field. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.11.0