@@ -824,6 +824,7 @@ static bool csiphy_is_gen2(u32 version)
bool ret = false;
switch (version) {
+ case CAMSS_615:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
@@ -905,6 +906,10 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->offset = 0x800;
switch (csiphy->camss->res->version) {
+ case CAMSS_615:
+ regs->lane_regs = &lane_regs_qcs615[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_qcs615);
+ break;
case CAMSS_845:
regs->lane_regs = &lane_regs_sdm845[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
@@ -339,6 +339,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
return sink_code;
}
break;
+ case CAMSS_615:
case CAMSS_660:
case CAMSS_7280:
case CAMSS_8x96:
@@ -1969,6 +1970,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
int ret = 8;
switch (vfe->camss->res->version) {
+ case CAMSS_615:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
@@ -515,6 +515,187 @@ static const struct camss_subdev_resources vfe_res_8x96[] = {
}
};
+static const struct camss_subdev_resources csiphy_res_615[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = { "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = { "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = { "csiphy2", "csiphy2_timer" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
+static const struct camss_subdev_resources csid_res_615[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "cphy_rx_src", "vfe0_cphy_rx", "vfe0_csid" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333, 384000000 },
+ { 320000000, 540000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "cphy_rx_src", "vfe1_cphy_rx", "vfe1_csid" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333, 384000000 },
+ { 320000000, 540000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "cphy_rx_src", "vfe_lite_cphy_rx", "vfe_lite_csid" },
+ .clock_rate = { { 269333333, 384000000 },
+ { 269333333, 384000000 },
+ { 320000000, 540000000 } },
+ .reg = { "csid_lite" },
+ .interrupt = { "csid_lite" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+};
+
+static const struct camss_subdev_resources vfe_res_615[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "camnoc_axi", "cpas_ahb", "slow_ahb_src",
+ "soc_ahb", "vfe0", "vfe0_axi"},
+ .clock_rate = { { 0 },
+ { 0 },
+ { 80000000 },
+ { 80000000 },
+ { 37500000, 40000000 },
+ { 360000000, 432000000, 540000000, 600000000 },
+ { 265000000, 426000000 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "camnoc_axi", "cpas_ahb", "slow_ahb_src",
+ "soc_ahb", "vfe1", "vfe1_axi"},
+ .clock_rate = { { 0 },
+ { 0 },
+ { 80000000 },
+ { 80000000 },
+ { 37500000, 40000000 },
+ { 360000000, 432000000, 540000000, 600000000 },
+ { 265000000, 426000000 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "camnoc_axi", "cpas_ahb", "slow_ahb_src",
+ "soc_ahb", "vfe_lite" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 80000000 },
+ { 80000000 },
+ { 37500000, 40000000 },
+ { 360000000, 432000000, 540000000, 600000000 } },
+ .reg = { "vfe_lite" },
+ .interrupt = { "vfe_lite" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
+static const struct resources_icc icc_res_qcs615[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "hf_0_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_660[] = {
/* CSIPHY0 */
{
@@ -3753,6 +3934,20 @@ static const struct camss_resources msm8996_resources = {
.link_entities = camss_link_entities
};
+static const struct camss_resources qcs615_resources = {
+ .version = CAMSS_615,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_615,
+ .csid_res = csid_res_615,
+ .vfe_res = vfe_res_615,
+ .icc_res = icc_res_qcs615,
+ .icc_path_num = ARRAY_SIZE(icc_res_qcs615),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_615),
+ .csid_num = ARRAY_SIZE(csid_res_615),
+ .vfe_num = ARRAY_SIZE(vfe_res_615),
+ .link_entities = camss_link_entities
+};
+
static const struct camss_resources sdm660_resources = {
.version = CAMSS_660,
.csiphy_res = csiphy_res_660,
@@ -3865,6 +4060,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
+ { .compatible = "qcom,qcs615-camss", .data = &qcs615_resources },
{ .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
@@ -77,6 +77,7 @@ enum pm_domain {
};
enum camss_version {
+ CAMSS_615,
CAMSS_660,
CAMSS_7280,
CAMSS_8x16,
Populate CAMSS with qcs615 specific hooks. Signed-off-by: Wenmeng Liu <quic_wenmliu@quicinc.com> --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 5 + drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 196 +++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 4 files changed, 204 insertions(+)