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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/eswin,sdhci-eic7700.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ESWIN EIC7700 SoC SDHCI controller
+
+maintainers:
+ - Shuang Liang <liangshuang@eswincomputing.com>
+ - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+allOf:
+ - $ref: /schemas/mmc/mmc-controller.yaml#
+
+properties:
+ compatible:
+ const: eswin,eic7700-emmc-sdhci
+
+ reg:
+ maxItems: 1
+ description: Common configuration registers
+ "#address-cells":
+ const: 1
+ "#size-cells":
+ const: 1
+
+ interrupts:
+ maxItems: 1
+
+ assigned-clocks:
+ maxItems: 1
+ description: should contain "core_clk" phandle + clock-specifier pairs.
+
+ assigned-clock-rates:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ description: handles to clock for the sdhci controller.
+
+ clock-names:
+ minItems: 2
+ description: the name of each clock.
+
+ clock-output-names:
+ maxItems: 1
+
+ '#clock-cells':
+ enum: [0]
+ description:
+ With this property in place we will export one clock
+ representing the Card Clock. These clocks are expected to be
+ consumed by our PHY.
+
+ resets:
+ description: resets to be used by the controller.
+
+ reset-names:
+ description: names of the resets listed in resets property in the same order.
+
+ bus-width:
+ enum: [4, 8]
+ description: for emmc bus-width is 8, for sdio bus-width is 4.
+
+ eswin,hsp_sp_csr:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: hsp_sp_csr regs to be used by the controller.
+ items:
+ - description: phandle to HSP_SP_CSR register block
+ - description: status register offset
+ - description: control register offset
+ - description: configuration register offset
+
+ eswin,syscrg_csr:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: syscrg_csr regs to be used by the controller.
+ items:
+ - description: phandle to SYS_CRG_CSR register block
+ - description: status register offset
+ - description: control register offset
+ - description: configuration register offset
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - assigned-clocks
+ - assigned-clock-rates
+ - clocks
+ - clock-names
+ - clock-output-names
+ - resets
+ - reset-names
+ - bus-width
+ - eswin,hsp_sp_csr
+ - eswin,syscrg_csr
+
+unevaluatedProperties: false
+
+examples:
+ - |
+
+ sdhci_emmc: mmc@50450000 {
+ compatible = "eswin,eic7700-emmc-sdhci";
+ reg = <0x50450000 0x10000>;
+ interrupt-parent = <&plic>;
+ interrupts = <79>;
+ clocks = <&clock 554>, <&clock 546>;
+ clock-names = "clk_xin", "clk_ahb";
+ assigned-clocks = <&clock 554>;
+ assigned-clock-rates = <200000000>;
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0>;
+
+ resets = <&reset 7 (1 << 6)>,
+ <&reset 7 (1 << 3)>,
+ <&reset 7 (1 << 19)>,
+ <&reset 7 (1 << 23)>;
+ reset-names = "txrx_rst", "phy_rst", "prstn", "arstn";
+
+ core-clk-reg = <0x51828160>;
+ disable-cqe-dcmd;
+ bus-width = <8>;
+ non-removable;
+ mmc-hs400-1_8v;
+ max-frequency = <200000000>;
+ eswin,hsp_sp_csr = <&hsp_sp_csr 0x1038 0x508 0x50c>;
+ eswin,syscrg_csr = <&sys_crg 0x160 0x148 0x14c>;
+ status = "disabled";
+ };