Message ID | 20250511203546.139788-6-richard.henderson@linaro.org |
---|---|
State | New |
Headers | show
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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22fc7544d86sm49955095ad.47.2025.05.11.13.35.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 May 2025 13:35:51 -0700 (PDT) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, schwab@linux-m68k.org Subject: [PATCH v6 05/24] target/m68k: Update FPSR for FMOVECR Date: Sun, 11 May 2025 13:35:27 -0700 Message-ID: <20250511203546.139788-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250511203546.139788-1-richard.henderson@linaro.org> References: <20250511203546.139788-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org |
Series |
target/m68k: fpu improvements
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expand
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diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index deae94b0ee..e63fd3ec11 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -425,6 +425,7 @@ void HELPER(ftst)(CPUM68KState *env, FPReg *val) void HELPER(fconst)(CPUM68KState *env, FPReg *val, uint32_t offset) { val->d = fpu_rom[offset]; + HELPER(ftst)(env, val); } typedef int (*float_access)(CPUM68KState *env, uint32_t addr, FPReg *fp,
This instruction sets CC and EXC bits just like any other. So far we do not properly emulate inexact for the various rom entries, but we can certainly update CC correctly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/m68k/fpu_helper.c | 1 + 1 file changed, 1 insertion(+)